Friday, May 10th 2019
AMD Ryzen 3000 "Zen 2" a Memory OC Beast, DDR4-5000 Possible
AMD's 3rd generation Ryzen (3000-series) processors will overcome a vast number of memory limitations faced by older Ryzen chips. With Zen 2, the company decided to separate the memory controller from the CPU cores into a separate chip, called "IO die". Our resident Ryzen memory guru Yuri "1usmus" Bubliy, author of DRAM Calculator for Ryzen, found technical info that confirms just how much progress AMD has been making.
The third generation Ryzen processors will be able to match their Intel counterparts when it comes to memory overclocking. In the Zen 2 BIOS, the memory frequency options go all the way up to "DDR4-5000", which is a huge increase over the first Ryzens. The DRAM clock is still linked to the Infinity Fabric (IF) clock domain, which means at DDR4-5000, Infinity Fabric would tick at 5000 MHz DDR, too. Since that rate is out of reach for IF, AMD has decided to add a new 1/2 divider mode for their on-chip bus. When enabled, it will run Infinity Fabric at half the DRAM actual clock (eg: 1250 MHz for DDR4-5000).
This could turn into an additional selling point for AMD X570 chipset motherboards, as they'll have a memory frequency headroom advantage over boards based on older chipsets as their BIOS will include not just the increased memory clock limit, but also the divider mode. Of course this doesn't mean that you can just magically overclock any memory kit to these 5 GHz speeds - it's probable that only the best of the best modules will be able to get close to these speeds.
1usmus also discovered that the platform adds a SoC OC mode and VDDG voltage control. We've heard from several sources that AMD invested heavily in improving memory compatibility, especially in the wake of Samsung discontinuing its B-die DRAM chips.
The third generation Ryzen processors will be able to match their Intel counterparts when it comes to memory overclocking. In the Zen 2 BIOS, the memory frequency options go all the way up to "DDR4-5000", which is a huge increase over the first Ryzens. The DRAM clock is still linked to the Infinity Fabric (IF) clock domain, which means at DDR4-5000, Infinity Fabric would tick at 5000 MHz DDR, too. Since that rate is out of reach for IF, AMD has decided to add a new 1/2 divider mode for their on-chip bus. When enabled, it will run Infinity Fabric at half the DRAM actual clock (eg: 1250 MHz for DDR4-5000).
1usmus also discovered that the platform adds a SoC OC mode and VDDG voltage control. We've heard from several sources that AMD invested heavily in improving memory compatibility, especially in the wake of Samsung discontinuing its B-die DRAM chips.
112 Comments on AMD Ryzen 3000 "Zen 2" a Memory OC Beast, DDR4-5000 Possible
It is not like IF is so fast anyway, according to AMD it runs at 42GB/s at 1333Mhz (or 2666 memory clock) according to
fuse.wikichip.org/news/1064/isscc-2018-amds-zeppelin-multi-chip-routing-and-packaging/
and that is very close to what memory benchmarks show for memory alone clocked at 3000Mhz. And yet, IF must also handle inter-CCX communication and PCIEx access - all that is overloading it's capacity.
Running it at twice the speed would be very good for performance if not power budget and yes I suppose AMD was not able to do so with ZEN/ZEN+, but I had hoped for ZEN2 to make it so.
Stating that "DDR-5000MHz is possible" simply based on the available bios options is silly and makes no favors to anyone, the least to AMD. The same way you could state that with the current generation Ryzen CPUs DDR-4133MHz is possible, or that on Intel Coffee Lake Refresh parts DDR-5500MHz is possible. In reality of course, most current generation Ryzen users still struggle reaching higher than 3466MHz and the same way the typical best case scenario for daily use on Intel platforms is roughly 4133MHz or less (mostly due to the DRAM PCB or MB PCB signaling limits).
Actually both current gen. Ryzens already support up to DDR-8466MHz by their Phy design, but lets no let the facts to get in the way of fabricating the "news".
As I said, reporting BS like this (and the majority of other Zen 2 related rumors) is not in anyones interests.
Matisse will no doubt bring good improvements in most areas (incl. memory speeds), but everyone should keep their expectations at sane levels regardless.
If w1zzard was dead, he'd be spinning in his grave... :(
As I said before, in my previous post. It seems Infinity Fabric will require at least 100 GB/s Bandwidth bidirectional in order to have enough to feed the 7nm Chiplets and the larger 14nm IO die.
I was under the impression the limiting factor for Infinity Fabric was the fact it was tied to the IMC. I still believe that's the case and the issue overall.
The intention is not to provide higher SDF bandwidth through higher frequency, but to allow higher MEMCLK frequencies (at a cost) to provide sufficient memory bandwidth.
Zen 2 is a wide core, and even Intel Xeons with 256-bit memory interface (QCH) become bandwidth starved in certain 256-bit workloads (not to mention 512-bit ones, hence SKL-SP uses 384-bit HCH memory config).
That's all I know about Zen2. No idea if there's one or two CCXes on that die.
Well that is what I read once that's it's possible all by moving everything on that 14nm I/O and keeping the CPU chipsets separate. Who knows really.
CCX is - as its name says - a core complex. In Zen it contains 4 cores and L3 cache (when looking at it on a high level). In a Zen/Zen+ chip die there are two such CCXs connected to Scalable Data Fabric (SDF) that we can characterize as IF hub where everything in the CPU connects to - CCXs, memory controllers, IO Hub. There is only one CCX configuration, while individual cores can be disabled in it there will not be multiple CCX configurations in the same generation. There are good reasons for expecting CCXs to remain at 4 cores in Zen 2.
Cores per die and cores per package are decidedly different from architectural features.
Amount of cores in Zen 2 CCX that we do not know is important because cores inside CCX can very quickly communicate with each other but communication with cores in a different CCX (even when it is on the same die) takes longer as it goes through IF connections.
It's just that I read somewhere in a previous article (Pre ZEN+ release), where the author speculated that one possible reason for utilizing this ZEN2 design approach was to potentially benefit from customizable 7nm Chiplets.
Anyhow, your explanation is clarity enough. Thank You,
There are some negatives as well. IF links between dies is slightly slower in its current form and does use more power. Whether chiplet design adds complexity to the package is not sure yet but it is likely. With memory controller in the I/O die, memory is inevitably further away from the CPU cores, increasing latency. How much and how AMD has mitigated that - we will see soon.
Customizable chiplets can be a huge boon for custom market - consoles primarily. Maybe (a big maybe) for laptops. On desktop as we know it, customizable chiplets in terms of adding a GPU for an APU does not look like too good of a solution. With I/O Die, memory is far away and GPU is very dependent on memory (usually more bandwidth than latency but still). AM4 does not have enough space or pins to add HBM or some direct connected RAM. TR4/SM3 are unlikely candidates for integrated GPU.
There are a lot of thoughts being shared about stacked dies but with current CPU parts (including 7nm), power density will be a huge problem.