Max(IT)tbh the “next big thing” should be Alder Lake, not Rocket Lake.


Let’s be honest: it almost was a paper launch with skyrocket prices for Zen 3.
I don’t know about new zeland, but here in Europe it is very difficult to find one at a decent price.

phanbueyWell... they hit 5Ghz on 14nm++++++ which we know they can do quite easily. Let's see if Alder Lake hits 5Ghz at 10nm.

Fierce GuppyWell, what's a decent price? This OK? Considering that you guys suffer more with higher taxes on stuff, it's probably a decent price.

Max(IT)It is one of the best prices in Europe... if you consider UK as part of the Europe (which is not...).
By the way that website is one of the best, but for some items they don’t ship outside UK

Fierce GuppyThe UK is not part of the European Union. It will always be a part of Europe by dint of its geographical location. In any case, the offer is not availble to you if you're not a UK resident. But if you knew someone in the UK that might do you a favour....

AnarchoPrimitivHere comes the Ryzen 5000 XT series on 7nm EUV (improved node)...willing to bet on it

Max(IT)tbh the “next big thing” should be Alder Lake, not Rocket Lake.

Max(IT)yep... I was speaking about not being in Europe in a commercial way, not geographically :D

theoneandonlymrkYep well 6800s most geforce's n in fact most GPU are scarce in the UK a rx580 sells for 220£ new still.
Plenty of intel CPU but few others in stock and favourite ones like 5900x aren't about anymore.
Oh to be rich.

dragontamer5788I think ARM has an advantage on decoder width. That's the only weak point of the x86 ISA I can think of.

x86 requires a byte-by-byte decoder, because you have 2-byte, 3-byte, 4-byte... 15-byte instructions (some of which are macro-op fused and/or micro-op split). ARM standardized upon 4-byte instructions with an occasional 8-byte macro-op fused. That means if you want to perform 4-wide decoding (and assume an average of 4-bytes per instruction), you need 64-parallel decoders: one for every byte (byte0, byte1, byte2) of the cache line.

ARM on the other hand is always 4-bytes or 8-bytes at a time (in the case of macro-op fused operations). Which means for a 64-byte decoder, ARM only need 16-parallel decoders: knowing there's no 2-byte or 3-byte instructions that could be "in-between". Just hypothetically speaking of course, I dunno really how these things are organized.

Anyway: Apple M1 shot a broadside at the x86 camp with their 8-wide decoder. I do think its relevant to bring up. However, ARM Neoverse is still only 4-wide decoding. It hasn't really been proven yet that an ultra-wide decoder (like Apple's M1) is really the best path forward.

Vya DomusI mean most of the performance that's worth extracting through ILP sits in loops and those don't put pressure on the decode stage because you'll keep hitting the instruction cache anyway which is colossal on something like M1. Actually the more I think about it the more absurd Apple's design choices appear to me.

dragontamer5788Well, the uOp cache could be used for other registers, or L1 cache instead. So I'm not sure of the existence of the uOp cache is favorable to your argument.

Vya DomusIt's really, really, unlikely for a real world single program to have it's instructions pushed out of the micro-op cache. I am not saying it doesn't happen but the micro-op cache is typically the least of your worries.

dragontamer5788Oh, what I'm saying is that the M1 has an advantage, because its decoder is 8-wide, while Intel / AMD has a disadvantage, because their uOp caches are only 6-wide. Instead of having a uOp cache, the M1 spent its transistors on more L1 cache and a larger register-file.

dragontamer5788Oh, what I'm saying is that the M1 has an advantage, because its decoder is 8-wide, while Intel / AMD has a disadvantage, because their uOp caches are only 6-wide. Instead of having a uOp cache, the M1 spent its transistors on more L1 cache and a larger register-file.

The M1 can fit 192kB into its L1 i-cache, which performs a bit faster than the Intel/AMD uOp cache thanks to 8-way decoding. Intel / AMD only have 48kB i-L1 (for Rocket Lake) or 32kB i-L1 (AMD Zen 3), and smaller than that for its uOp cache.

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EDIT: I should say "Seems to have an advantage". Its not very clear if Apple's big decoder is a good strategy yet IMO. But its interesting, and worth keeping an eye on. Especially because it seems like an area that may be harder to implement into x86.

Vya DomusI really doubt that a micro-op cache is that much of an expensive mechanism to add definitely not comparable to the size and power of a larger L1 I-cache, they probably didn't add one because it just wasn't required, you're really gonna tell me that Apple is that conscious about their transistor budget ? :) And after all a lot of CPUs out there don't have one either, it's a pretty recent addition.

What I am also saying it that I haven't actually seen any evidence that such a wide decoder is actually worth it. Wide decode means a lot of delay in the circuitry which means poor clock speed scaling.

bluetriangleclockThere goes AMD's brief lead in gaming. :roll:

But it was never a real lead since the Ryzen 5000 launch was a paper launch.

theoneandonlymrkRight, sorry misquoted you which is a shame since your comedy famnboi stomping, over an unreleased chips scores on a shit benchmark just got more attention.