Tuesday, April 12th 2022
"Navi 31" RDNA3 Sees AMD Double Down on Chiplets: As Many as 7
Way back in January 2021, we heard a spectacular rumor about "Navi 31," the next-generation big GPU by AMD, being the company's first logic-MCM GPU (a GPU with more than one logic die). The company has a legacy of MCM GPUs, but those have been a single logic die surrounded by memory stacks. The RDNA3 graphics architecture that the "Navi 31" is based on, sees AMD fragment the logic die into smaller chiplets, with the goal of ensuring that only those specific components that benefit from the TSMC N5 node (6 nm), such as the number crunching machinery, are built on the node, while ancillary components, such as memory controllers, display controllers, or even media accelerators, are confined to chiplets built on an older node, such as the TSMC N6 (6 nm). AMD had taken this approach with its EPYC and Ryzen processors, where the chiplets with the CPU cores got the better node, and the other logic components got an older one.
Greymon55 predicts an interesting division of labor on the "Navi 31" MCM. Apparently, the number-crunching machinery is spread across two GCD (Graphics Complex Dies?). These dies pack the Shader Engines with their RDNA3 compute units (CU), Command Processor, Geometry Processor, Asynchronous Compute Engines (ACEs), Rendering Backends, etc. These are things that can benefit from the advanced 5 nm node, enabling AMD to the CUs at higher engine clocks. There's also sound logic behind building a big GPU with two such GCDs instead of a single large GCD, as smaller GPUs can be made with a single such GCD (exactly why we have two 8-core chiplets making up a 16-core Ryzen processors, and the one of these being used to create 8-core and 6-core SKUs). The smaller GCD would result in better yields per wafer, and minimize the need for separate wafer orders for a larger die (such as in the case of the Navi 21).
Besides two GCDs, there are four MCDs (memory controller dies). Greymon55 predicts that these could be built on the 6 nm (TSMC N6) node, a slightly more advanced node than N7 (7 nm). Each MCD controls two 32-bit memory paths, controlling two memory chips, or 64-bit of the memory bus width. Four such MCDs make up 256-bit. For ASICs with just one GCD, there could be three MCDs (192-bit), or even just two (128-bit). The MCD packs the GDDR6 memory controller, as well as its PHY. There could also be exotic fixed-function hardware for features such as memory compression and ECC (latter being available on Pro SKUs).
The third and final kind of die is the I/O Die. On both Socket AM4 and SP3 processors, the IOD serves as town-square, connecting all the CPU chiplets, and crams memory, PCIe, and other platform I/O. On "Navi 31," the IOD could pack all the components that never need overclocking—these include the PCI-Express switch (which connects the GPU to the system), the Display CoreNext (DCN) component that controls the various display outputs; and perhaps even the Video CoreNext (VCN), which packs the media accelerators. At this point it's not known which node the IOD is built on.
The ether connecting all 7 chiplets on the "Navi 31" MCM is Infinity Fabric. IFOP (Infinity Fabric over package), as implemented on EPYC "Milan" or the upcoming "Genoa" processors, has shown that its wiring isn't of high enough density that it needs an interposer, and can make do with the fiberglass substrate. Such will be the case with "Navi 31," too. The MCDs will wire out to the GDDR6 memory devices just the way current GPUs do it, so will the IOD, while all the chiplets talk to each other over IFOP.
Sources:
Greymon55 (Twitter), VideoCardz
Greymon55 predicts an interesting division of labor on the "Navi 31" MCM. Apparently, the number-crunching machinery is spread across two GCD (Graphics Complex Dies?). These dies pack the Shader Engines with their RDNA3 compute units (CU), Command Processor, Geometry Processor, Asynchronous Compute Engines (ACEs), Rendering Backends, etc. These are things that can benefit from the advanced 5 nm node, enabling AMD to the CUs at higher engine clocks. There's also sound logic behind building a big GPU with two such GCDs instead of a single large GCD, as smaller GPUs can be made with a single such GCD (exactly why we have two 8-core chiplets making up a 16-core Ryzen processors, and the one of these being used to create 8-core and 6-core SKUs). The smaller GCD would result in better yields per wafer, and minimize the need for separate wafer orders for a larger die (such as in the case of the Navi 21).
The third and final kind of die is the I/O Die. On both Socket AM4 and SP3 processors, the IOD serves as town-square, connecting all the CPU chiplets, and crams memory, PCIe, and other platform I/O. On "Navi 31," the IOD could pack all the components that never need overclocking—these include the PCI-Express switch (which connects the GPU to the system), the Display CoreNext (DCN) component that controls the various display outputs; and perhaps even the Video CoreNext (VCN), which packs the media accelerators. At this point it's not known which node the IOD is built on.
The ether connecting all 7 chiplets on the "Navi 31" MCM is Infinity Fabric. IFOP (Infinity Fabric over package), as implemented on EPYC "Milan" or the upcoming "Genoa" processors, has shown that its wiring isn't of high enough density that it needs an interposer, and can make do with the fiberglass substrate. Such will be the case with "Navi 31," too. The MCDs will wire out to the GDDR6 memory devices just the way current GPUs do it, so will the IOD, while all the chiplets talk to each other over IFOP.
40 Comments on "Navi 31" RDNA3 Sees AMD Double Down on Chiplets: As Many as 7
I've personally bought 4 RTX cards since they were launched and I'm still yet to see a situation where any game's RT effects are worth the performance hit. The ones where RTX are used the most look the best but also suffer the highest performance penalties, and I'd rather just game at higher resolutions and refresh rates. It's not as if RTX reflections or shadows are perfect, they're just a bit more convincing than the baked or screen-space method most games without RTX support use.
Screen-space ambient occlusion looks pretty terrible when cranked up too high, whilst RTX AO looks convincing but is extremely expensive for such a subtle feature. Every other RTX feature I can happily do without.
I think we'll generally see a bigger use of vapor chambers instead of the cheaper cold plate options and cooling will probably not be a problem for reasonable cards (none of that 400w+ nonsense), but I won't hold my breath on any price reductions (you save some on the MCM chip, but then spend it on the package and interconnect, etc..)
A monolithic die can only make direct contact with 2-3 heatpipes, depending on the size of the die and heatpipes. Additional heatpipes that don't contact the die don't do an awful lot.
MCM designs spread the dies out, meaning that different heatpipes can cover different dies and the result is that in, say, a five heatpipe design, all five heatpipes are being useful and no single die is using silly amounts of power that could overwhelm the specific heatpipe(s) that it's making contact with.
A vapor chamber is the obvious answer but they cost more and in even when paying silly money for GPUs these days, manufacturers don't want to spend any more than they absolutely have to. If a heatpipe is adequate, that is what you're going to get and if you're willing to spend more on cooling they'll instead try to sell you a ridiculous thing with an AIO water loop attached to it because their markup on that is fantastic.
And then there's also the rumored other dies (they're talking about 7 chiplets total which seems excessive for a first iteration of the technology) so I think the logical solution should be vapor chambers all around
It's why the intels can overclock and through at 300W, while the 5800x cant be cooled at 150W.
My 5800X is easily cooled at the 142W stock boost limit. I have one on water and it's a piece of cake, previously it was using a decade-old NH-U12 (effictively the same as the modern redux version) and never broke 80C. The dozens of 5950X machines at work are air-cooled too, and they're basically two 5800X sharing a single cooler....
custom water, lapped, liquid metal... nothings made mine work as you claim it does.
80C? sure, but what clock speed? What type of load?
Fire up AVX load and see if you're even close to the 5.05GHz these chips are capable of, and you're more likely to be around 4.4GHz
The 5950x is not the same, as it shares that wattage over double the surface area.
IIRC it was plateauing in the high-seventies, like 78-79C when fully loaded with a Cinbench r23 for the 10-minute default multi-threaded test with a very old noctua cooler NH-U12 and a bequiet low-RPM fan which maxed out at 1500rpm.
Now on an Alphacool loop with a 140+360 radiator it boosts to 4575MHz at ~65C. Granted, it's a sample size of one, but presumably so is your chip. I also don't use AVX workloads and those always run slower anyway, even on Intel.
The 5950X rendernodes of which I have a much larger sample size are on air and they crunch full load 24/7 at work at about 4.35GHz. That's using an NH-U14S SP3 which results in 90C at ~175W CPU power draw. I set a high TDP for those manually, and then reduced the throttle temperature to 90C so they'll basically operate at that temperature and use whatever power the NH-U14S can cool to 90C.
But based on your response to the other guy I think we are in agreement.
AMD Navi 31 GCD (Graphics Complex Die) is reportedly 350 mm²+ in size - VideoCardz.com
The cards are just around the corner now.
AMD Navi 3X RDNA3 GPU family highlighted in new fan-made renders - VideoCardz.com