This speculative logic makes no sense in either the VC or XDA articles. Nothing "makes it pretty clear it will feature 2 Zen 4 and four Zen 4c cores". Zen 4c features the same 16MB L3 per 8 cores as Zen 4 in Phoenix. The 8MB L3 is also no surprise, AMD has halved L3 on its quad core APUs many times before. The loss of L2 also corresponds to it being a 4-core.

The only confirmation is that it's a 6-core + 4CU with the known smaller die size. The Videocardz article admits that the hybrid arch is still a "might", the XDA article goes off the rails rambling about how the fact that AMD has never made a pure 6-core before means that 4 of the cores must be Zen 4c..........what? I made some paint shenanigans a few PHX-2 articles back to show that simply cutting out 2 cores+L3 and a bunch of CUs is roughly in the ballpark of PHX-2's size.

The Zen 4c Bergamo CPUs also have a MUCH lower ~3GHz clock envelope which fits into the guesstimated freq hit that Zen 4c's floorplan rearranging was said to incur (think it was either Cuttress or someone at Chips&Cheese). The Phoenix-2 product is clocked similarly to regular Phoenix. So far there still hasn't been any clear indication that AMD has intended Zen 4c to be anything other than a space-optimization/moar cores measure specifically for the layout of the [chiplet] CCD.

tabascosauzThis speculative logic makes no sense in either the VC or XDA articles. Nothing "makes it pretty clear it will feature 2 Zen 4 and four Zen 4c cores". Zen 4c features the same 16MB L3 per 8 cores as Zen 4 in Phoenix. The 8MB L3 is also no surprise, AMD has halved L3 on its quad core APUs many times before. The loss of L2 also corresponds to it being a 4-core.

The only confirmation is that it's a 6-core + 4CU with the known smaller die size. The Videocardz article admits that the hybrid arch is still a "might", the XDA article goes off the rails rambling about how the fact that AMD has never made a pure 6-core before means that 4 of the cores must be Zen 4c..........what? I made some paint shenanigans a few PHX-2 articles back to show that simply cutting out 2 cores+L3 and a bunch of CUs is roughly in the ballpark of PHX-2's size.

The Zen 4c Bergamo CPUs also have a MUCH lower clock envelope which fits into the guesstimated freq hit that Zen 4c's floorplan rearranging was said to incur (think it was either Cuttress or someone at Chips&Cheese). The Phoenix-2 product is clocked similarly to regular Phoenix. So far there still hasn't been any clear indication that AMD has intended Zen 4c to be anything other than a space-optimization/moar cores measure specifically in the layout of the [chiplet] CCD.

This is what we get when TPU "news" is allowed to become reposts of reposts of reposts of someone talking out of their a**. I've long expected better, given that this is (ostensibly) a PC tech site whereas so many of the quoted "sources" are not.

AssimilatorThis is what we get when TPU "news" is allowed to become reposts of reposts of reposts of someone talking out of their a**. I've long expected better, given that this is (ostensibly) a PC tech site whereas so many of the quoted "sources" are not.

Same. I feel that things have gone downhill, but that applies to everything the world over unfortunately. :(

Zen 4c has less L3 per core as implemented in the 16c CCD vs the standard Zen 4 8c CCD but both CCDs have 32MB in total.

When placing that core layout into a monolithic design there is nothing known about the L3 cache. We know that usually AMD cuts L3 in the APUs so using Zen 4c or standard Zen 4 will come down to desired clocks vs desired power usage vs die size. A mix might be in play to have 1 or 2 high clocking cores and the rest lower clocking but lower power use but we have zero info on details and probably won't know until either AMD divulge it or we get a die shot.

Really though a 6c monolithic die using standard Zen 4 would be 23mm for the 6 cores + L2 with the rest taken up with L3, IO, GPU etc.

A 6c hybrid of Zen 4 and Zen4c in a 2/4 config would reduce that to 17.6mm so the saving is not really that great in terms of die area. That means the main reason for such a design would be power savings which would probably be pretty good given how power efficient Bergamo is.

btk2k2Zen 4c has less L3 per core as implemented in the 16c CCD vs the standard Zen 4 8c CCD but both CCDs have 32MB in total.

When placing that core layout into a monolithic design there is nothing known about the L3 cache. We know that usually AMD cuts L3 in the APUs so using Zen 4c or standard Zen 4 will come down to desired clocks vs desired power usage vs die size. A mix might be in play to have 1 or 2 high clocking cores and the rest lower clocking but lower power use but we have zero info on details and probably won't know until either AMD divulge it or we get a die shot.

Really though a 6c monolithic die using standard Zen 4 would be 23mm for the 6 cores + L2 with the rest taken up with L3, IO, GPU etc.

A 6c hybrid of Zen 4 and Zen4c in a 2/4 config would reduce that to 17.6mm so the saving is not really that great in terms of die area. That means the main reason for such a design would be power savings which would probably be pretty good given how power efficient Bergamo is.

I don't even think power efficiency factors into this. Regular Zen 4 as used in Phoenix is plenty efficient already in the 2-3GHz range (everyday laptop range) that we know Zen 4c to operate in. I highly doubt there are magical, generational perf/W gains lying in plain sight just from a rearrangement of Zen 4.

It's not hard to see why Bergamo is efficient: any of AMD's CPU chiplet products has significant I/O die and interconnect power overhead that detracts from the practical efficiency of the actual Zen cores, EPYC is no exception (even worse due to more IFOP and more IODs). You're always operating with a constant handicap from the non-CCD things, so just get each CCD to do more without increasing non-CCD power. With double core count and all cores operating well within the flat area of their V-F curve, efficiency automatically increases significantly. None of those considerations apply to AMD's current and past APUs, they have no more SOC power draw than monolithic Intel.

So from any standpoint it just doesn't make much sense to sub in Zen 4c in Phoenix. Efficiency doesn't make it worth it, space savings aren't worth it - at least for Intel E-cores make sense because P-cores are so massive, but Zen 4 isn't.

btk2k2the saving is not really that great in terms of die area.

I don't agree here. A 23% saving in die area really *is* that great, we're talking about the 4nm node that's scarce and expensive. Intel made two variants of desktop Alder Lake die for that same reason (215.25 mm2 and 157.74 mm2, which is 27% less).

But I agree that a hybrid design is highly unlikely, and would create issues that only a good Thread Director can (help) solve.

I've seen many opinions that thread scheduling on AMD's hybrid cores would be trivial because "IPC is the same". Huh? Sure it's the same - as long as the code doesn't use L3 cache much. And even if it were the same, the performance obviously wouldn't be the same, and this is what counts in scheduling.

Another thing to note here is that AMD would have four levels of performance in a single hybrid chip: Zen 4 without HT, 4c without HT, 4 with HT, and 4c with HT (in descending order, probably). That's a hard nut to crack. Intel "only" has three levels: P without HT, E, and P with HT.

WirkoI don't agree here. A 23% saving in die area really *is* that great, we're talking about the 4nm node that's scarce and expensive. Intel made two variants of desktop Alder Lake die for that same reason (215.25 mm2 and 157.74 mm2, which is 27% less).

But I agree that a hybrid design is highly unlikely, and would create issues that only a good Thread Director can (help) solve.

I've seen many opinions that thread scheduling on AMD's hybrid cores would be trivial because "IPC is the same". Huh? Sure it's the same - as long as the code doesn't use L3 cache much. And even if it were the same, the performance obviously wouldn't be the same, and this is what counts in scheduling.

Another thing to note here is that AMD would have four levels of performance in a single hybrid chip: Zen 4 without HT, 4c without HT, 4 with HT, and 4c with HT (in descending order, probably). That's a hard nut to crack. Intel "only" has three levels: P without HT, E, and P with HT.

It would also matter even more if the C cores were lower clocked for one reason or another.

I know in the past, AMD has had more improvements they wanted to make before releasing a new architecture, but eventually they have to pause development so they can start mass production. I wonder if that's what these C cores also have, where AMD was able to make some more improvements to shrink die sizes beyond just less L3. If these were never intended to clock as high or consume as much power, then it's quite possible other changes could be made in the name of space savings. Zen4 is efficient, but AMD shot past the peak of that efficiency curve in order to squeeze out more performance. You can significantly reduce the TDP on Zen 4 and still get a lot of performance, but that's not the default design. Zen 4 is designed to get hot. 95C is no problem. I'm curious if these C cores have a lower temperature threshold. We won't know until we can get some deep dives.

How did rumours about mixed-cores in APUs come about in the first place?
Has there been any reliable evidence that this could be the case?

WirkoI don't agree here. A 23% saving in die area really *is* that great, we're talking about the 4nm node that's scarce and expensive. Intel made two variants of desktop Alder Lake die for that same reason (215.25 mm2 and 157.74 mm2, which is 27% less).

But I agree that a hybrid design is highly unlikely, and would create issues that only a good Thread Director can (help) solve.

I've seen many opinions that thread scheduling on AMD's hybrid cores would be trivial because "IPC is the same". Huh? Sure it's the same - as long as the code doesn't use L3 cache much. And even if it were the same, the performance obviously wouldn't be the same, and this is what counts in scheduling.

Another thing to note here is that AMD would have four levels of performance in a single hybrid chip: Zen 4 without HT, 4c without HT, 4 with HT, and 4c with HT (in descending order, probably). That's a hard nut to crack. Intel "only" has three levels: P without HT, E, and P with HT.

A smaller APU is fine but the difference between a standard 6c and a 2/4 hybrid version is about 6mm or 5%. Not nothing but power would be a bigger factor.

AMD is planning to launch an APU that uses a combination of Zen 4 and Zen 4c cores the same way Intel uses P-cores and E-cores in its CPUs, and AMD has even confirmed it would eventually launch such a chip.

When did AMD confirm this?!

In my correspondence with AMD, several key details about this small APU (presumably Phoenix 2) were confirmed [...] While AMD did not mention that this smaller APU would be a hybrid design, it's highly likely that it is for architectural reasons.

Which one is it?! Did AMD confirm it or not?!

It's pure speculation.

tabascosauzThe Zen 4c Bergamo CPUs also have a MUCH lower ~3GHz clock envelope which fits into the guesstimated freq hit that Zen 4c's floorplan rearranging was said to incur

We don't know the upper (hard) limit on 4c wrt clock speed, whatever AMD released was for servers & designed for peak density/efficiency among other things. We need retail chips to see what it's really capable of.

T1beriuWhen did AMD confirm this?!

Which one is it?! Did AMD confirm it or not?!

It's pure speculation.

Read this part of TPU interviewand make of it whatever you wish. My understanding is "no hybrid designs but maybe 4c for laptops one day".

WirkoRead this part of TPU interviewand make of it whatever you wish. My understanding is "no hybrid designs but maybe 4c for laptops one day".

It's no brainer that Zen c cores could feature in Athlon CPUs, and maybe some Ryzen in future. They roll out stuff step-by-step. Don't expect a flood of products with c cores.

WirkoI've seen many opinions that thread scheduling on AMD's hybrid cores would be trivial because "IPC is the same". Huh? Sure it's the same - as long as the code doesn't use L3 cache much. And even if it were the same, the performance obviously wouldn't be the same, and this is what counts in scheduling.

That's exactly the point that I believe a lot of people really miss. What really matters for hybrid designs is not IPC or anything like that, but performance.

We have already seen plenty of mobile SoCs with that, having high-clocked A53 and lower clocked A53. Same core IPC(not counting cluster cache difference) but very different performance target.

A Zen4 core that can run AVX-512 code at 2GHz is wildly different than one that can run the same code at 4GHz.

In any case, Intel also has issues with the Ring bus clocks, as it's coupled to E-cores clock, so it will drag down the performance of P-cores. This might also affect AMD as they might really not want to run separate clocks for each L3 and at the same time, they might also be forced to clock it down to the lowest clock.

If so, this would add to Scheduler complexity, as waking up a Zen4c core, could effectively lower system performance in certain situations.

WirkoRead this part of TPU interviewand make of it whatever you wish. My understanding is "no hybrid designs but maybe 4c for laptops one day".

I know about that interview. My question is how does that interview confirm that Ryzen 7440U is hybrid design?

The interview clearly reads that AMD has no intention of deploying hybrid designs any time soon.

I am wondering where those rumours are coming from. A bit silly...

They night release all c-core SKUs in Athlon or lower Ryzen range, but we will need to wait and see. For now, c-cores is all about density in cloud server segment.

Core density, density, and once more density.

Tek-CheckIt's no brainer that Zen c cores could feature in Athlon CPUs, and maybe some Ryzen in future. They roll out stuff step-by-step. Don't expect a flood of products with c cores.

AMD so far has preferred to reuse older Zens on older nodes for low end, 4-core CPUs and APUs. But maybe they are changing the course. I guess it all depends on how many 5nm/4nm kilowafers they can get and at what price.

persondbIn any case, Intel also has issues with the Ring bus clocks, as it's coupled to E-cores clock, so it will drag down the performance of P-cores.

Didn't Intel fix that in Raptor Lake?