Thursday, June 20th 2024
TSMC Begins Experimenting with Rectangular Panel-Like Chip Packaging
TSMC is working on a new advanced chip packaging technology that uses rectangular panel-like substrates instead of the traditional circular wafers, according to a Nikkei report citing sources. This new approach would allow more chips to be placed on a single substrate. TSMC is reportedly experimenting with rectangular substrates measuring 515 mm by 510 mm, providing more than three times the usable area compared to current 12-inch wafers. Using a rectangular-shaped wafer can potentially eliminate more of the incomplete chips found on the edges of current circular ones. While this may sound simple, it would actually require a radical change to the entire manufacturing process.
While the research is still in its early stages and may take several years to reach mass production, it represents a major technological shift for TSMC. The company has responded to Nikkei's inquiry by stating that they are closely monitoring advancements in advanced packaging technologies, including panel-level packaging. This development could potentially give TSMC an edge in meeting future chip demands, however, Intel and Samsung are also testing this new approach.
Sources:
TrendForce, Nikkei
While the research is still in its early stages and may take several years to reach mass production, it represents a major technological shift for TSMC. The company has responded to Nikkei's inquiry by stating that they are closely monitoring advancements in advanced packaging technologies, including panel-level packaging. This development could potentially give TSMC an edge in meeting future chip demands, however, Intel and Samsung are also testing this new approach.
25 Comments on TSMC Begins Experimenting with Rectangular Panel-Like Chip Packaging
Something like AMDs CCD on the current standard is getting ~900 dies on a standard wafer. Hits nearly 4000 on the new standard.
It would also be a lot more attractive to people like AMD/nVidia if they can do agreements on a per wafer basis as well
That's what used to make all the little circuits, transistors and so on in silicon so it works.
patentimages.storage.googleapis.com/e0/7f/4a/a23e6910bf7b5c/US9111745.pdf
Actually you can already see rectangular wafers from the Cerebras wafer scale chip. Im not sure if it's cut from a circular one as i haven't looked into it but it should give a visual representation of what a rectangular wafer would look like. It's smaller at 215x215 compared to the 515x510 mentioned in the article.
This coupled with advancements like backside power delivery, High-NA etc should ensure continues yields into the 1.x nm era.
Is the lack of this technology at present the reason for AMD's Navi 4C chiplet design failure?
www.techpowerup.com/312364/amd-navi-4c-gpu-detailed-shader-engines-are-their-own-chiplets?cp=2
It is far more likely and logical that AMD simply sacrificed high end RDNA 4 design to give the limited CoWoS allocation to MI3XX series.
Once TSMC expands it's capacity and the AI hype dies down RDNA 5 can hopefully use CoWoS again in 2026.
I would hate consumer GPU's to be stuck with monolithic designs the same way they are restricted to GDDR memory with HBM reserved for enterprise use only.
You know that when you plan such a design, you must be well aware how you will make it in the reality.The thing is that there is no evidence that HBM in any form would help. Actually, there are other solutions - narrow memory buses, with large L3 caches (Infinity Cache), and cheapest available GDDR.
You have a problem with the shaders' utilisation, and the efficient usage of the available memory bandwidth.
You can put a 2-3TB/s memory communication, but if the shaders can feed them to only 30%, then you simply waste resources.
OTH, most consumers would be fine on 10 year old hardware, and a chip specked like those now costs $50 (intel n100)
Anyway if this new technique does work and makes it into mass production, competition will make the prices fluctuate in comsumers benefit after a while for sure it's just market forces.
compare that to cutting out squares of equal size
To make things more complicated, even a Si interposer has its own substrate (the word means "bottom layer"), upon which layers with wires are built.Agreed. HBM is for those who need, and can pay for, very high density and lower consumption (in joules/bit). That's how you stuff 100 or 200 AMD or NV accelerators in a single rack.Hm, that's possible, yes, as Si substrates without transistors don't demand the highest purity crystals or best uniformity.
*first wafer i found googling no clue what's on it.
you would need a very precise cutting machine to not damage the other tiles as the cutting thing would have to go right over them
But whatever the process is, the cost of the discarded, unexposed parts of the wafer should be vastly lower than the cost of fully processed parts, that is, the dice, or dies. Semianalysis had an article with costs breakdown but I can't find it right now.
So maybe the waste is a small issue really - until your substrates become very big compared to 300 mm.
This is how the silicon ingot looks, and after being sliced.
The actual die wafers are still going to be round, because they're sliced pure silicon crystals. You don't get to choose the shape of the crystals, that's predetermined by the polarity and bond arrangement of silicon atoms.