As demand for ever-growing AI compute power continues to rise and manufacturing advanced nodes becomes more difficult, packaging is undergoing its golden era of development. Today's advanced accelerators often rely on TSMC's CoWoS modules, which are built on wafer cuts measuring no more than 120 × 150 mm in size. In response to the need for more space, TSMC has unveiled plans for CoPoS, or "Chips on Panel on Substrate," which could expand substrate dimensions to 310 × 310 mm and beyond. By shifting from round wafers to rectangular panels, CoPoS offers more than five times the usable area. This extra surface makes it possible to integrate additional high-bandwidth memory stacks, multiple I/O chiplets and compute dies in a single package. It also brings panel-level packaging (PLP) to the fore. Unlike wafer-level packaging (WLP), PLP assembles components on large, rectangular panels, delivering higher throughput and lower cost per unit. Systems with PLP will be actually viable for production runs and allow faster iterations over WLP.

TSMC will establish a CoPoS pilot line in 2026 at its Visionchip subsidiary. In 2027, the pilot facility will focus on refining the process, to meet partner requirements by the end of the year. Mass production is projected to begin between the end of 2028 and early 2029 at TSMC's Chiayi AP7 campus. That site, chosen for its modern infrastructure and ample space, is also slated to host production of multi-chip modules and System-on-Wafer technologies. NVIDIA is expected to be the launch partner for CoPoS. The company plans to leverage the larger panel area to accommodate up to 12 HBM4 chips alongside several GPU chiplets, offering significant performance gains for AI workloads. At the same time, AMD and Broadcom will continue using TSMC's CoWoS-L and CoWoS-R variants for their high-end products. Beyond simply increasing size, CoPoS and PLP may work in tandem with other emerging advances, such as glass substrates and silicon photonics. If development proceeds as planned, the first CoPoS-enabled devices could reach the market by late 2029.

TSMC has declared that it has no immediate plans to build fabrication plants in the Middle East, reinforcing its strategy to focus on regions where customer demand is strong. Last week's rumors that TSMC might establish a gigafab in the United Arab Emirates have been dismissed by company executives as baseless. CEO CC Wei explained that an expansion into the Gulf does not fit with TSMC's model of locating factories near its largest clients. With ongoing investments in the US, Japan, and Germany, the company aims to serve technology leaders and automotive manufacturers more effectively. Wei added that, without a solid local customer base, building in the Middle East would be impractical. At the same time, TSMC indicated it is reviewing wafer pricing. Fluctuations in the Taiwanese dollar and changing global tariffs were cited as factors under consideration.

According to Wei, long-term agreements could include modest price increases, especially for advanced process nodes, where research and development costs and manufacturing challenges are rising. Looking ahead, TSMC confirmed that the upcoming A14 1.4 nm node wafers are expected to be priced around $45,000 each. This would represent a 50 percent increase over the current 2 nm wafers, which cost about $30,000 apiece. Production of the 1.4 nm node is projected to begin around 2028. Only TSMC's top-tier customers are likely to reserve capacity for this cutting-edge node in its early stages. As demand for advanced semiconductors rises, the company's approach to pricing and geographic focus will be key to maintaining its leadership in the global foundry market.

At this year's Technology Symposium, TSMC unveiled an engaging multi-year roadmap for its packaging technologies. TSMC's strategy splits into two main categories: Advanced Packaging and System-on-Wafer. Back in 2016, CoWoS-S debuted with four HBM stacks paired to N16 compute dies on a 1.5× reticle-limited interposer, which was an impressive feat at the time. Fast forward to 2025, and CoWoS-S now routinely supports eight HBM chips alongside N5 and N4 compute tiles within a 3.3× reticle budget. Its successor, CoWoS-R, increases interconnect bandwidth and brings N3-node compatibility without changing that reticle constraint. Looking toward 2027, TSMC will launch CoWoS-L. First up are large N3-node chiplets, followed by N2-node tiles, multiple I/O dies, and up to a dozen HBM3E or HBM4 stacks—all housed within a 5.5× reticle ceiling. It's hard to believe that eight HBM stacks once sounded ambitious—now they're just the starting point for next-gen AI accelerators inspired by AMD's Instinct MI450X and NVIDIA's Vera Rubin.

Integrated Fan-Out, or InFO, adds another dimension with flexible 3D assemblies. The original InFO bridge is already powering AMD's Instinct cards. Later this year, InFO-POP (package-on-package) and InFO-2.5D arrive, promising even denser chip stacking and unlocking new scaling potential on a single package, away from the 2D and 2.5D packaging we were used to, going into the third dimension. On the wafer scale, TSMC's System-on-Wafer lineup—SoW-P and SoW-X—has grown from specialized AI engines into a comprehensive roadmap mirroring logic-node progress. This year marks the first SoIC stacks from N3 to N4, with each tile up to 830 mm² and no hard limit on top-die size. That trajectory points to massive, ultra-dense packages, which is exactly what HPC and AI data centers will demand in the coming years.

Global semiconductor materials market revenue increased 3.8% to $67.5 billion in 2024, SEMI, the global industry association representing the electronics design and manufacturing supply chain, reported today in its Materials Market Data Subscription (MMDS). The recovery of the overall semiconductor market as well as the increasing demand for advanced materials for high-performance compute and high-bandwidth memory manufacturing supported 2024 materials revenue growth.

Wafer fabrication materials revenue increased 3.3% to $42.9 billion in 2024, while packaging materials revenue grew 4.7% to $24.6 billion last year. The chemical mechanical planarization (CMP), photoresist, and photoresist ancillaries segments experienced strong double-digit growth driven by increased complexity and number of processing steps required for advanced DRAM, 3D NAND flash and leading-edge logic integrated circuits (ICs). All semiconductor materials segments, except for silicon and silicon-on-insulator (SOI), registered year-on-year increases. The demand for silicon, particularly in the trailing edge segment, remained weak in 2024 as the industry continued to work through excess inventory, resulting in a 7.1% decline in silicon revenue in 2024.

As the US works to bring more semiconductor manufacturing back home, the machines needed to turn silicon into the world's most advanced processors are becoming pricier and harder to get, thanks to tariffs. Foundries building new fabs report that the specialized equipment they rely on, everything from extreme ultraviolet (EUV) lithography steppers to chemical vapor deposition chambers, carries a roughly 15% premium compared with similar gear sold overseas. Several forces are at play. The raw materials, high‑grade quartz for vacuum enclosures, and exotic metal alloys for precision optics have climbed in price. At the same time, key components like ultra‑accurate motion stages and alignment sensors are in short supply, sometimes stretching lead times for critical subsystems well beyond 18 months. For a fab racing to move from a 7 nm to a 5 nm process, those delays can mean missing tight ramp‑up targets and pushing out product launches.

Smaller chipmakers feel the squeeze the hardest. With fewer orders to negotiate volume discounts, second‑tier foundries may see their capital budgets balloon by 20 percent or more. In response, some are taking a mixed approach, sourcing commoditized tools such as oxidation furnaces and rapid thermal processors from multiple suppliers while reserving single‑vendor deals for high‑stakes systems like EUV scanners. Government support through the CHIPS Act offers a partial safety net, helping to subsidize capital expenditures. Yet even with grants and tax credits, the challenges will remain. Success will hinge on tight coordination between fabs, equipment makers, and policymakers to tame rising costs, shorten delivery schedules, and keep America's chip renaissance on track.

Vietnam's government has approved its first wafer fab facility, with an investment of 12.8 trillion VND (approximately $500 million). The first phase of the facility, scheduled for completion by 2030, is designed to manufacture specialized chips for defense, AI, and other high-tech applications. The project will receive government backing through direct funding—covering up to 30% of the total investment, capped at 10 trillion VND—and tax incentives. A special steering committee headed by the Prime Minister has been tasked with overseeing the project's execution and resource allocation. The new fab is a critical component of Vietnam's long-term semiconductor strategy, a phased approach toward building a domestic ecosystem for chip design, manufacturing, and testing. The current investment is modest compared to the typical costs of advanced wafer fabs, which can reach up to $50 billion.

Nonetheless, the project is a foundational, one-step-at-the-time move intended to spur further investments and technology transfer. Vietnamese officials have reportedly engaged in discussions with major international chip manufacturers—including US, South Korea, and Taiwan entities, such as GlobalFoundries and Powerchip Semiconductor Manufacturing Corp—to explore potential collaborative opportunities. Vietnam already hosts 174 semiconductor-related projects, predominantly focused on chip packaging and testing, in which global companies like Intel and Amkor have established significant operations. The second phase, from 2030-2040, envisions Vietnam emerging as a worldwide center for electronics and semiconductors. By expanding to at least 200 design companies, establishing two semiconductor chip manufacturing plants, and creating 15 packaging and testing facilities, the country intends to gradually develop independent semiconductor product design and production capabilities.

Intel's 18A node, often referred to as Intel's silver lining, has just produced tangible result. In a LinkedIn post of Intel's engineering manager Pankaj Marria, we learn that Intel's 18A node is now being produced in initial wafer lots for testing and evaluation by Intel's customers. This means that Intel's 18A node PDK is officially in version 1.0, and customers are already using that PDK for testing of custom chips. "The Eagle has landed," noted the post, referring to the node development as a major milestone for a node developed and made in US. There were even posters with the same slogans being brought up, meaning that possible customers are also happy with inital test runs. With high-volume manufacturing slated for second half of 2025, we could even see 18A HVM going before initial targets.

Intel's leadership transition to CEO Lip-Bu Tan has overlapped with a recalibration of corporate messaging around the foundry business. Tan's internal communication explicitly frames Intel's strategy as a dual-track approach that maintains both product development and foundry services under unified corporate governance. This position counters speculation regarding potential foundry spinoff scenarios, though it doesn't categorically exclude future structural changes. Previous industry rumors had outlined potential joint venture configurations involving TSMC and major US semiconductor firms, including AMD, Broadcom, and NVIDIA, taking equity positions in a separate foundry entity. While such arrangements remain theoretically viable, Tan's emphasis on fab strategic importance aligns with predecessor Pat Gelsinger's manufacturing-centric vision, suggesting continuity in Intel's Foundry and Product model despite market pressure.

Samsung aims to create 1,000-layer NAND by 2030 relying on its new "multi-BV" NAND design. The Bell reports that this plan involves stacking four wafers to overcome structural limits. Wafer bonding technology plays a crucial role in this progress and Samsung intends to use it to break the 1,000-layer barrier. Samsung Electronics DS division CTO, Song Jae-hyuk, pointed out that wafer bonding allows separate production of peripheral and cell wafers before joining them into one semiconductor. The Bell says this technology will likely appear first in Samsung's 10th-gen NAND (V10), while industry experts think a single wafer can hold about 500 NAND layers when implementing only cell structures. In the past, Samsung has used the COP (Cell on Peripheral) technique, a method that places the peripheral circuit on one wafer, with NAND cells stacked on top. However, as NAND layers grow, the lower peripheral parts face more pressure potentially affecting reliability.

Samsung's plan involves working with China's YMTC, which should offer a hybrid bonding patent for V10 NAND. ZDNet reports that the South Korean tech company will start making its V10 NAND in large quantities in the second half of 2025, with about 420-430 layers. Besides wafer bonding, Samsung adds other technologies to its NAND plan. The Bell points out that cold etching using molybdenum, and other new ideas will start with 400-layer NAND and play a key part in growing to 1,000 layers. Samsung isn't alone in trying to create ultra-high-layer NAND products. Japan's Kioxia also wants to reach this goal through its "multi-stack CBA" (CMOS Bonded to Array) technology. The company's plan is even bolder hoping to sell 1,000-layer 3D NAND by 2027.

Intel has successfully deployed two advanced ASML High-NA Twinscan EXE:5000 EUV lithography systems at its D1 development facility near Hillsboro, Oregon, processing approximately 30,000 wafers in a single quarter. The High-NA EUV systems, each reportedly valued at $380 million, represent a substantial improvement over previous lithography tools, achieving resolution down to 8 nm with a single exposure compared to the 13.5 nm resolution of current Low-NA systems. Early operational data indicates these machines are approximately twice as reliable as previous EUV generations, addressing reliability challenges that previously hampered Intel's manufacturing progress. The ability to accomplish with a single exposure what previously required three exposures and approximately 40 processing steps has been reduced to just "single digit" processing steps.

Intel has historically been an early adopter of high-NA EUV lithography, a much more aggressive strategy than its competitors like TSMC, which manufactures its advanced silicon using low-NA EUV tools. The company plans to utilize these systems for its upcoming 14A chip manufacturing process, though no specific mass production date has been announced. While ASML classifies these Twinscan EXE:5000 systems as pre-production tools not designed for high-volume manufacturing, Intel's extensive wafer processing is more of a test bed. The early adoption provides Intel with valuable development opportunities across various High-NA EUV manufacturing aspects, including photomask glass, pellicles, and specialized chemicals that could establish future industry standards. Intel's current 18A node is utilizing Low-NA lithography tools, where Intel is only exploring High-NA with it for testing, before moving on to 14A high-volume manufacturing with High-NA EUV.

Earlier in the year, we heard about TSMC being ahead of the game with its speculated trial production run of cutting-edge 2 nm (N2) silicon. Taiwan's premier foundry company is reportedly prepping its Baoshan and Kaohsiung plants for full-on manufacturing of next-gen chips. The latest insider whispers propose that TSMC is making "rapid" progress on the 2 nm (N2) front, as company engineers have moved onto an "intensive" trial production phase. Taiwan's Economic Daily News has picked up on compelling projections from industry moles; the Hsinchu Baoshan facility's current monthly production capacity is (allegedly) around 5000 to 10,000 2 nm wafers. The other 2 nm-specialist site—Kaohsiung—has reportedly moved into a small-scale appraisal phase.

TSMC declined to comment on recently leaked data points, but they released a general statement (to UDN), emphasizing that: "(our) 2 nm process technology is progressing well and will go into mass production as scheduled in the second half of this year." The Baoshan plant could ramp up to 25,000 2 nm wafers per month, once it moves into a mass production phase. Combined with the same estimated output from its sister site (Kaohsiung), insiders reckon that the combined total could reach 50,000 units per month. Following a predicted successful "second phase" transition, TSMC's most advanced facilities have a "chance" to pump out 80,000 2 nm parts (combined total). The latest murmurs suggest that this milestone could be achieved by the end of 2025. Industry watchdogs believe that Apple will have first access dibs on TSMC's upcoming cutting-edge offerings.

The global semiconductor manufacturing industry closed 2024 with strong fourth quarter results and solid year-on-year (YoY) growth across most of the key industry segments, SEMI announced today in its Q4 2024 publication of the Semiconductor Manufacturing Monitor (SMM) Report, prepared in partnership with TechInsights. The industry outlook is cautiously optimistic at the start of 2025 as seasonality and macroeconomic uncertainty may impede near-term growth despite momentum from strong investments related to AI applications.

After declining in the first half of 2024, electronics sales bounced back later in the year resulting in a 2% annual increase. Electronics sales grew 4% YoY in Q4 2024 and are expected to see a 1% YoY increase in Q1 2025 impacted by seasonality. Integrated circuit (IC) sales rose by 29% YoY in Q4 2024 and continued growth is expected in Q1 2025 with a 23% increase YoY as AI-fueled demand continues boosting shipments of high-performance computing (HPC) and datacenter memory chips.

Earlier this week, Taiwan experienced a magnitude 6.4 earthquake—this seismic event interrupted manufacturing activities at several TSMC chip-making facilities. As a precaution, foundry employees in both Central and Southern Taiwan were evacuated. Production resumed fairly quickly following inspections of crucial infrastructure—no major damage to facilities or equipment was noted. The latest reports suggest that a relatively minor number of TSMC wafers have been affected by the recent quake, while some recalibration of instrumentation is required to get things back on track.

Inside sources reckon that up to 20,000 wafers (possibly 10,000 at a minimum) could be scrapped—assessments are reportedly still underway, but a small proportion of client shipments could be disrupted. News articles point to this total being spread across three affected locations. Fab 18 is a key 3 nm production hub—situated in Taiwan's Southern Science Park, Tainan's Fab 14 specializes in 4 nm and 5 nm processes, and Fab 8 (Hsinchu) takes care of 200 nm. Industry experts believe that TSMC will bounce back quickly, and that the damaged wafer count represents a minor dent in the proverbial armor—on a good day, manufacturing output can reach up to 37,000 units.

The U.S. Department of Commerce will award GlobalWafers America and MEMC, LLC, U.S. subsidiaries of Taiwan-based GlobalWafers Co., Ltd., up to $406 million in direct funding under the CHIPS Incentives Program's Funding Opportunity for Commercial Fabrication Facilities.

The award will support planned investments of $4 billion in advanced semiconductor wafer manufacturing facilities in Sherman, Texas and St. Peters, Missouri. The Department will disburse the funds based on GWA's and MEMC's completion of project milestones over a multi-year timeframe.

Global sales of total semiconductor manufacturing equipment by original equipment manufacturers (OEMs) are forecast to set a new industry record, reaching $113 billion in 2024, growing 6.5% year-on-year, SEMI announced today in its Year-End Total Semiconductor Equipment Forecast - OEM Perspective at SEMICON Japan 2024. Semiconductor manufacturing equipment growth is expected to continue in the following years, reaching new records of $121 billion in 2025 and $139 billion in 2026, supported by both the front-end and back-end segments.

"Three consecutive years of projected growth in investments in semiconductor manufacturing reflect the vital role our industry plays in underpinning the global economy and advancing technology innovation," said Ajit Manocha, SEMI president and CEO. "Since our July 2024 forecast, the outlook for 2024 semiconductor equipment sales has brightened, especially with stronger-than-expected investments from China and in AI-related sectors. Together with our forecast extension through 2026, it highlights the robust growth drivers across segments, applications, and regions."

Intel Corporation today announced that Eric Meurice, former president, chief executive officer and chairman of ASML Holding N.V., and Steve Sanghi, chairman and interim chief executive officer of Microchip Technology Inc., have been appointed to Intel's board of directors, effective immediately. Both will serve as independent directors.

"Eric and Steve are highly respected leaders in the semiconductor industry whose deep technical expertise, executive experience and operational rigor make them great additions to the Intel board," said Frank D. Yeary, interim executive chair of the Intel board. "As successful CEOs with proven track records of creating shareholder value, they will bring valuable perspectives to the board as the company delivers on its priorities for customers in Intel Products and Intel Foundry, while driving greater efficiency and improving profitability."

Worldwide silicon wafer shipments increased 5.9% quarter-over-quarter to 3,214 million square inches (MSI) in the third quarter of 2024 and registered 6.8% growth from the 3,010 million square inches recorded during the same quarter last year, the SEMI Silicon Manufacturers Group (SMG) reported in its quarterly analysis of the silicon wafer industry.

"The third quarter wafer shipment results continued the upward trend which started in the second quarter of this year," said Lee Chungwei (李崇偉), Chairman of SEMI SMG and Vice President and Chief Auditor at GlobalWafers. "Inventory levels have declined throughout the supply chain but generally remain high. Demand for advanced wafers used for AI continues to be strong. However, the silicon wafer demand for automotive and industrial uses continues to be muted, while the demand for silicon used for handset and other consumer products has seen some areas of improvement. As a result, 2025 is likely to continue upward trends, but total shipments are not yet expected to return to the peak levels of 2022."

After announcing the world's first 300-millimeter gallium nitride (GaN) power wafer and opening the world's largest 200-millimeter silicon carbide (SiC) power fab in Kulim, Malaysia, Infineon Technologies AG has unveiled the next milestone in semiconductor manufacturing technology. Infineon has reached a breakthrough in handling and processing the thinnest silicon power wafers ever manufactured, with a thickness of only 20 micrometers and a diameter of 300 millimeters, in a high-scale semiconductor fab. The ultra-thin silicon wafers are only a quarter as thick as a human hair and half as thick as current state-of-the-art wafers of 40-60 micrometers.

"The world's thinnest silicon wafer is proof of our dedication to deliver outstanding customer value by pushing the technical boundaries of power semiconductor technology," said Jochen Hanebeck, CEO at Infineon Technologies. "Infineon's breakthrough in ultra-thin wafer technology marks a significant step forward in energy-efficient power solutions and helps us leverage the full potential of the global trends decarbonization and digitalization. With this technological masterpiece, we are solidifying our position as the industry's innovation leader by mastering all three relevant semiconductor materials: Si, SiC and GaN."

Global shipments of silicon wafers are projected to decline 2% in 2024 to 12,174 million square inches (MSI) with a strong rebound of 10% delayed until 2025 to reach 13,328 MSI as wafer demand continues to recover from the downcycle, SEMI reported today in its annual silicon shipment forecast.

Strong silicon wafer shipment growth is expected to continue through 2027 to meet increasing demand related to AI and advanced processing, driving improved fab utilization rate for global semiconductor production capacity. Moreover, new applications in advanced packaging and high-bandwidth memory (HBM) production, which require additional wafers, are contributing to the rising need for silicon wafers. Such applications include temporary or permanent carrier wafers, interposers, device separation into chiplets, and memory/logic array separation.

Amkor Technology, Inc. and TSMC announced today that the two companies have signed a memorandum of understanding to collaborate and bring advanced packaging and test capabilities to Arizona, further expanding the region's semiconductor ecosystem.

Amkor and TSMC have been closely collaborating to deliver high volume, leading-edge technologies for advanced packaging and testing of semiconductors to support critical markets such as high-performance computing and communications. Under the agreement, TSMC will contract turnkey advanced packaging and test services from Amkor in their planned facility in Peoria, Arizona. TSMC will leverage these services to support its customers, particularly those using TSMC's advanced wafer fabrication facilities in Phoenix. The close collaboration and proximity of TSMC's front-end fab and Amkor's back-end facility will accelerate overall product cycle times.

Infineon Technologies AG today announced that the company has succeeded in developing the world's first 300 mm power gallium nitride (GaN) wafer technology. Infineon is the first company in the world to master this groundbreaking technology in an existing and scalable high-volume manufacturing environment. The breakthrough will help substantially drive the market for GaN-based power semiconductors. Chip production on 300 mm wafers is technologically more advanced and significantly more efficient compared to 200 mm wafers, since the bigger wafer diameter offers 2.3 times more chips per wafer.

GaN-based power semiconductors find fast adoption in industrial, automotive, and consumer, computing & communication applications, including power supplies for AI systems, solar inverters, chargers and adapters, and motor-control systems. State-of-the art GaN manufacturing processes lead to improved device performance resulting in benefits in end customers' applications as it enables efficiency performance, smaller size, lighter weight, and lower overall cost. Furthermore, 300 mm manufacturing ensures superior customer supply stability through scalability.

Taiwanese semiconductor giant TSMC is reportedly planning to increase its wafer prices by up to 10% in 2025, according to a Morgan Stanley note cited by investor Eric Jhonsa. The move comes as demand for cutting-edge processors in smartphones, PCs, AI accelerators, and HPC continues to surge. Industry insiders reveal that TSMC's state-of-the-art 4 nm and 5 nm nodes, used for AI and HPC customers such as AMD, NVIDIA, and Intel, could see up to 10% price hikes. This increase would push the cost of 4 nm-class wafers from $18,000 to approximately $20,000, representing a significant 25% rise since early 2021 for some clients and an 11% rise from the last price hike. Talks about price hikes with major smartphone manufacturers like Apple have proven challenging, but there are indications that modest price increases are being accepted across the industry. Morgan Stanley analysts project a 4% average selling price increase for 3 nm wafers in 2025, which are currently priced at $20,000 or more per wafer.

Mature nodes like 16 nm are unlikely to see price increases due to sufficient capacity. However, TSMC is signaling potential shortages in leading-edge capacity to encourage customers to secure their allocations. Adding to the industry's challenges, advanced chip-on-wafer-on-substrate (CoWoS) packaging prices are expected to rise by 20% over the next two years, following previous increases in 2022 and 2023. TSMC aims to boost its gross margin to 53-54% by 2025, anticipating that customers will absorb these additional costs. The impact of these price hikes on end-user products remains uncertain. Competing foundries like Intel and Samsung may seize this opportunity to offer more competitive pricing, potentially prompting some chip designers to consider alternative manufacturing options. Additionally, TSMC's customers could reportedly be unable to secure their capacity allocation without "appreciating TSMC's value."

TSMC is working on a new advanced chip packaging technology that uses rectangular panel-like substrates instead of the traditional circular wafers, according to a Nikkei report citing sources. This new approach would allow more chips to be placed on a single substrate. TSMC is reportedly experimenting with rectangular substrates measuring 515 mm by 510 mm, providing more than three times the usable area compared to current 12-inch wafers. Using a rectangular-shaped wafer can potentially eliminate more of the incomplete chips found on the edges of current circular ones. While this may sound simple, it would actually require a radical change to the entire manufacturing process.

While the research is still in its early stages and may take several years to reach mass production, it represents a major technological shift for TSMC. The company has responded to Nikkei's inquiry by stating that they are closely monitoring advancements in advanced packaging technologies, including panel-level packaging. This development could potentially give TSMC an edge in meeting future chip demands, however, Intel and Samsung are also testing this new approach.

TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company's 2024 North America Technology Symposium. TSMC debuted the TSMC A16 technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

This year marks the 30th anniversary of TSMC's North America Technology Symposium, and more than 2,000 attended the event, growing from less than 100 attendees 30 years ago. The North America Technology Symposium in Santa Clara, California kicks off TSMC Technology Symposiums around the world in the coming months. The symposium also features an "Innovation Zone," designed to highlight the technology achievements of our emerging start-up customers.

Arizona State University (ASU) and Deca Technologies (Deca), a premier provider of advanced wafer- and panel-level packaging technology, today announced a groundbreaking collaboration to create North America's first fan-out wafer-level packaging (FOWLP) research and development center.

The new Center for Advanced Wafer-Level Packaging Applications and Development is set to catalyze innovation in the United States, expanding domestic semiconductor manufacturing capabilities and driving advancements in cutting-edge fields such as artificial intelligence, machine learning, automotive electronics and high-performance computing.

Cerebras Systems, the pioneer in accelerating generative AI, and G42, the Abu Dhabi-based leading technology holding group, today announced the build of Condor Galaxy 3 (CG-3), the third cluster of their constellation of AI supercomputers, the Condor Galaxy. Featuring 64 of Cerebras' newly announced CS-3 systems - all powered by the industry's fastest AI chip, the Wafer-Scale Engine 3 (WSE-3) - Condor Galaxy 3 will deliver 8 exaFLOPs of AI with 58 million AI-optimized cores. The Cerebras and G42 strategic partnership already delivered 8 exaFLOPs of AI supercomputing performance via Condor Galaxy 1 and Condor Galaxy 2, each amongst the largest AI supercomputers in the world. Located in Dallas, Texas, Condor Galaxy 3 brings the current total of the Condor Galaxy network to 16 exaFLOPs.

"With Condor Galaxy 3, we continue to achieve our joint vision of transforming the worldwide inventory of AI compute through the development of the world's largest and fastest AI supercomputers," said Kiril Evtimov, Group CTO of G42. "The existing Condor Galaxy network has trained some of the leading open-source models in the industry, with tens of thousands of downloads. By doubling the capacity to 16exaFLOPs, we look forward to seeing the next wave of innovation Condor Galaxy supercomputers can enable." At the heart of Condor Galaxy 3 are 64 Cerebras CS-3 Systems. Each CS-3 is powered by the new 4 trillion transistor, 900,000 AI core WSE-3. Manufactured at TSMC at the 5-nanometer node, the WSE-3 delivers twice the performance at the same power and for the same price as the previous generation part. Purpose built for training the industry's largest AI models, WSE-3 delivers an astounding 125 petaflops of peak AI performance per chip.