Worldwide silicon wafer shipments increased 5.9% quarter-over-quarter to 3,214 million square inches (MSI) in the third quarter of 2024 and registered 6.8% growth from the 3,010 million square inches recorded during the same quarter last year, the SEMI Silicon Manufacturers Group (SMG) reported in its quarterly analysis of the silicon wafer industry.

"The third quarter wafer shipment results continued the upward trend which started in the second quarter of this year," said Lee Chungwei (李崇偉), Chairman of SEMI SMG and Vice President and Chief Auditor at GlobalWafers. "Inventory levels have declined throughout the supply chain but generally remain high. Demand for advanced wafers used for AI continues to be strong. However, the silicon wafer demand for automotive and industrial uses continues to be muted, while the demand for silicon used for handset and other consumer products has seen some areas of improvement. As a result, 2025 is likely to continue upward trends, but total shipments are not yet expected to return to the peak levels of 2022."

After announcing the world's first 300-millimeter gallium nitride (GaN) power wafer and opening the world's largest 200-millimeter silicon carbide (SiC) power fab in Kulim, Malaysia, Infineon Technologies AG has unveiled the next milestone in semiconductor manufacturing technology. Infineon has reached a breakthrough in handling and processing the thinnest silicon power wafers ever manufactured, with a thickness of only 20 micrometers and a diameter of 300 millimeters, in a high-scale semiconductor fab. The ultra-thin silicon wafers are only a quarter as thick as a human hair and half as thick as current state-of-the-art wafers of 40-60 micrometers.

"The world's thinnest silicon wafer is proof of our dedication to deliver outstanding customer value by pushing the technical boundaries of power semiconductor technology," said Jochen Hanebeck, CEO at Infineon Technologies. "Infineon's breakthrough in ultra-thin wafer technology marks a significant step forward in energy-efficient power solutions and helps us leverage the full potential of the global trends decarbonization and digitalization. With this technological masterpiece, we are solidifying our position as the industry's innovation leader by mastering all three relevant semiconductor materials: Si, SiC and GaN."

Global shipments of silicon wafers are projected to decline 2% in 2024 to 12,174 million square inches (MSI) with a strong rebound of 10% delayed until 2025 to reach 13,328 MSI as wafer demand continues to recover from the downcycle, SEMI reported today in its annual silicon shipment forecast.

Strong silicon wafer shipment growth is expected to continue through 2027 to meet increasing demand related to AI and advanced processing, driving improved fab utilization rate for global semiconductor production capacity. Moreover, new applications in advanced packaging and high-bandwidth memory (HBM) production, which require additional wafers, are contributing to the rising need for silicon wafers. Such applications include temporary or permanent carrier wafers, interposers, device separation into chiplets, and memory/logic array separation.

Amkor Technology, Inc. and TSMC announced today that the two companies have signed a memorandum of understanding to collaborate and bring advanced packaging and test capabilities to Arizona, further expanding the region's semiconductor ecosystem.

Amkor and TSMC have been closely collaborating to deliver high volume, leading-edge technologies for advanced packaging and testing of semiconductors to support critical markets such as high-performance computing and communications. Under the agreement, TSMC will contract turnkey advanced packaging and test services from Amkor in their planned facility in Peoria, Arizona. TSMC will leverage these services to support its customers, particularly those using TSMC's advanced wafer fabrication facilities in Phoenix. The close collaboration and proximity of TSMC's front-end fab and Amkor's back-end facility will accelerate overall product cycle times.

Infineon Technologies AG today announced that the company has succeeded in developing the world's first 300 mm power gallium nitride (GaN) wafer technology. Infineon is the first company in the world to master this groundbreaking technology in an existing and scalable high-volume manufacturing environment. The breakthrough will help substantially drive the market for GaN-based power semiconductors. Chip production on 300 mm wafers is technologically more advanced and significantly more efficient compared to 200 mm wafers, since the bigger wafer diameter offers 2.3 times more chips per wafer.

GaN-based power semiconductors find fast adoption in industrial, automotive, and consumer, computing & communication applications, including power supplies for AI systems, solar inverters, chargers and adapters, and motor-control systems. State-of-the art GaN manufacturing processes lead to improved device performance resulting in benefits in end customers' applications as it enables efficiency performance, smaller size, lighter weight, and lower overall cost. Furthermore, 300 mm manufacturing ensures superior customer supply stability through scalability.

Taiwanese semiconductor giant TSMC is reportedly planning to increase its wafer prices by up to 10% in 2025, according to a Morgan Stanley note cited by investor Eric Jhonsa. The move comes as demand for cutting-edge processors in smartphones, PCs, AI accelerators, and HPC continues to surge. Industry insiders reveal that TSMC's state-of-the-art 4 nm and 5 nm nodes, used for AI and HPC customers such as AMD, NVIDIA, and Intel, could see up to 10% price hikes. This increase would push the cost of 4 nm-class wafers from $18,000 to approximately $20,000, representing a significant 25% rise since early 2021 for some clients and an 11% rise from the last price hike. Talks about price hikes with major smartphone manufacturers like Apple have proven challenging, but there are indications that modest price increases are being accepted across the industry. Morgan Stanley analysts project a 4% average selling price increase for 3 nm wafers in 2025, which are currently priced at $20,000 or more per wafer.

Mature nodes like 16 nm are unlikely to see price increases due to sufficient capacity. However, TSMC is signaling potential shortages in leading-edge capacity to encourage customers to secure their allocations. Adding to the industry's challenges, advanced chip-on-wafer-on-substrate (CoWoS) packaging prices are expected to rise by 20% over the next two years, following previous increases in 2022 and 2023. TSMC aims to boost its gross margin to 53-54% by 2025, anticipating that customers will absorb these additional costs. The impact of these price hikes on end-user products remains uncertain. Competing foundries like Intel and Samsung may seize this opportunity to offer more competitive pricing, potentially prompting some chip designers to consider alternative manufacturing options. Additionally, TSMC's customers could reportedly be unable to secure their capacity allocation without "appreciating TSMC's value."

TSMC is working on a new advanced chip packaging technology that uses rectangular panel-like substrates instead of the traditional circular wafers, according to a Nikkei report citing sources. This new approach would allow more chips to be placed on a single substrate. TSMC is reportedly experimenting with rectangular substrates measuring 515 mm by 510 mm, providing more than three times the usable area compared to current 12-inch wafers. Using a rectangular-shaped wafer can potentially eliminate more of the incomplete chips found on the edges of current circular ones. While this may sound simple, it would actually require a radical change to the entire manufacturing process.

While the research is still in its early stages and may take several years to reach mass production, it represents a major technological shift for TSMC. The company has responded to Nikkei's inquiry by stating that they are closely monitoring advancements in advanced packaging technologies, including panel-level packaging. This development could potentially give TSMC an edge in meeting future chip demands, however, Intel and Samsung are also testing this new approach.

TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company's 2024 North America Technology Symposium. TSMC debuted the TSMC A16 technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

This year marks the 30th anniversary of TSMC's North America Technology Symposium, and more than 2,000 attended the event, growing from less than 100 attendees 30 years ago. The North America Technology Symposium in Santa Clara, California kicks off TSMC Technology Symposiums around the world in the coming months. The symposium also features an "Innovation Zone," designed to highlight the technology achievements of our emerging start-up customers.

Arizona State University (ASU) and Deca Technologies (Deca), a premier provider of advanced wafer- and panel-level packaging technology, today announced a groundbreaking collaboration to create North America's first fan-out wafer-level packaging (FOWLP) research and development center.

The new Center for Advanced Wafer-Level Packaging Applications and Development is set to catalyze innovation in the United States, expanding domestic semiconductor manufacturing capabilities and driving advancements in cutting-edge fields such as artificial intelligence, machine learning, automotive electronics and high-performance computing.

Cerebras Systems, the pioneer in accelerating generative AI, and G42, the Abu Dhabi-based leading technology holding group, today announced the build of Condor Galaxy 3 (CG-3), the third cluster of their constellation of AI supercomputers, the Condor Galaxy. Featuring 64 of Cerebras' newly announced CS-3 systems - all powered by the industry's fastest AI chip, the Wafer-Scale Engine 3 (WSE-3) - Condor Galaxy 3 will deliver 8 exaFLOPs of AI with 58 million AI-optimized cores. The Cerebras and G42 strategic partnership already delivered 8 exaFLOPs of AI supercomputing performance via Condor Galaxy 1 and Condor Galaxy 2, each amongst the largest AI supercomputers in the world. Located in Dallas, Texas, Condor Galaxy 3 brings the current total of the Condor Galaxy network to 16 exaFLOPs.

"With Condor Galaxy 3, we continue to achieve our joint vision of transforming the worldwide inventory of AI compute through the development of the world's largest and fastest AI supercomputers," said Kiril Evtimov, Group CTO of G42. "The existing Condor Galaxy network has trained some of the leading open-source models in the industry, with tens of thousands of downloads. By doubling the capacity to 16exaFLOPs, we look forward to seeing the next wave of innovation Condor Galaxy supercomputers can enable." At the heart of Condor Galaxy 3 are 64 Cerebras CS-3 Systems. Each CS-3 is powered by the new 4 trillion transistor, 900,000 AI core WSE-3. Manufactured at TSMC at the 5-nanometer node, the WSE-3 delivers twice the performance at the same power and for the same price as the previous generation part. Purpose built for training the industry's largest AI models, WSE-3 delivers an astounding 125 petaflops of peak AI performance per chip.

Global semiconductor capacity is expected to increase 6.4% in 2024 to top the 30 million *wafers per month (wpm) mark for the first time after rising 5.5% to 29.6 wpm in 2023, SEMI announced today in its latest quarterly World Fab Forecast report.

The 2024 growth will be driven by capacity increases in leading-edge logic and foundry, applications including generative AI and high-performance computing (HPC), and the recovery in end-demand for chips. The capacity expansion slowed in 2023 due to softening semiconductor market demand and the resulting inventory correction.

International Data Corporation (IDC) has upgraded its Semiconductor Market Outlook by calling a bottom and return to growth that accelerates next year. IDC raised its September 2023 revenue outlook from $518.8 billion to $526.5 billion in a new forecast. Revenue expectations for 2024 were also raised from $625.9 billion to $632.8 billion as IDC believes the U.S. market will remain resilient from a demand standpoint and China will begin recovering by the second half of 2024 (2H24).

IDC sees better semiconductor growth visibility as the long inventory correction subsides in two of the largest market segments: PCs and smartphones. Automotive and Industrials elevated inventory levels are expected to return to normal levels in 2H24 as electrification continues to drive semiconductor content over the next decade. Technology and large flagship product introductions will drive more semiconductor content and value across market segments in 2024 through 2026, including the introduction of AI PCs and AI Smartphones next year and a much-needed improvement in memory ASPs and DRAM bit volume.

Texas Instruments (TI) today broke ground on its new 300-mm semiconductor wafer fabrication plant (or "fab") in Lehi, Utah. Joined by Utah Governor Spencer Cox, state and local elected officials, as well as community leaders, TI President and Chief Executive Officer Haviv Ilan celebrated the first steps toward construction of the new fab, LFAB2, which will connect to the company's existing 300-mm wafer fab in Lehi. Once completed, TI's two Utah fabs will manufacture tens of millions of analog and embedded processing chips every day at full production.

"Today we take an important step in our company's journey to expand our manufacturing footprint in Utah. This new fab is part of our long-term, 300-mm manufacturing roadmap to build the capacity our customers will need for decades to come," said Ilan. "At TI, our passion is to create a better world by making electronics more affordable through semiconductors. We are proud to be a growing member of the Utah community, and to manufacture analog and embedded processing semiconductors that are vital for nearly every type of electronic system today."

The burgeoning AI market is significantly impacting TSMC's CoWoS (Chip on Wafer on Substrate) advanced packaging production capacity, causing it to overflow due to high demand from major companies like NVIDIA, AMD, and Amazon. To accommodate this, TSMC is in the process of expanding its production capacity by acquiring additional CoWoS machines from equipment manufacturers like Xinyun, Wanrun, Hongsu, Titanium, and Qunyi. These expansions are expected to be operational in the first half of the next year, leading to an increased monthly production capacity, potentially close to 30,000 pieces, enabling TSMC to cater to more AI-related orders. These endeavors to increase capacity are in response to the amplified demand for AI chips from their applications in various domains, including autonomous vehicles and smart factories.

Despite TSMC's active steps to enlarge its CoWoS advanced packaging production, the overwhelming client demand is driving the company to place additional orders with equipment suppliers. It has been indicated that NVIDIA is currently TSMC's largest CoWoS advanced packaging customer, accounting for 60% of its production capacity. Due to the surge in demand, companies like AMD, Amazon, and Broadcom are also placing urgent orders, leading to a substantial increase in TSMC's advanced process capacity utilization. The overall situation indicates a thriving scenario for equipment manufacturers with clear visibility of orders extending into the following year, even as they navigate the challenges of fulfilling the rapidly growing and immediate demand in the AI market.

Recently, the spot market for NAND Flash chips has seen a rise in active price inquiries for certain products, a movement driven by successful increases in wafer contract prices. TrendForce reports this uptick primarily stems from negotiations in late August between NAND Flash suppliers and key Chinese module makers. These discussions led to a new wafer contract that successfully boosted the price of 512 Gb wafers by approximately 10%.

Other suppliers have also raised prices for their comparable products, signaling a shift in supplier sentiment: they are now less inclined to finalize deals at lower prices. This change has contributed to a short-term surge in the wafer spot market. Nevertheless, whether this surge in procurement is supported by actual end-user demand remains uncertain, as these orders have arisen in reaction to adjustments in supply-side pricing.

Worldwide silicon wafer shipments increased 2.0% quarter-over-quarter to 3,331 million square inches in the second quarter of 2023, down 10.1% from the 3,704 million square inches recorded during the same quarter last year, the SEMI Silicon Manufacturers Group (SMG) reported in its quarterly analysis of the silicon wafer industry.

"The semiconductor industry continues to work through excess inventory in various market segments, necessitating that fabs operate below full capacity," said Anna-Riikka Vuorikari-Antikainen, Chairman of SEMI SMG and Chief Commercial Officer at Okmetic. "As a result, silicon wafer shipments are lagging their 2022 peak. Second-quarter wafer shipments held steady quarter-on-quarter with 300 mm showing quarterly growth among all wafer sizes."

TrendForce reports that OEMs have continued making concerted efforts to scale back production. However, given that the trajectory of market demand is still unclear, it's expected that the NAND Flash market will continue to be in a state of oversupply in 3Q23. Cautious inventory management by buyers is preventing a stabilization in NAND Flash prices even with an anticipated seasonal surge in demand for 2H23. TrendForce predicts that NAND Flash wafers will be the first to see a price hike in 3Q23 as prices for module products such as SSDs, eMMCs, and UFS will likely continue to fall due to tepid downstream demand. Consequently, the overall ASP of NAND Flash is forecast to continue dropping by about 3~8% in 3Q23, though a possibility exists prices may recover in 4Q23.

Client SSD: Although notebook shipments are expected to gradually recover in 3Q23, reversing an oversupply of SSD will continue to be challenging. Furthermore, a portion of suppliers have implemented aggressive promotions to secure customer orders and hit shipping targets in light of weakened demand and less-than-satisfactory order volumes from major clients, putting pressure on other suppliers. TrendForce estimates that the ASP of client SSDs will fall by 8~13% in the third quarter.

TrendForce reports that explosive growth in generative AI applications like chatbots has spurred significant expansion in AI server development in 2023. Major CSPs including Microsoft, Google, AWS, as well as Chinese enterprises like Baidu and ByteDance, have invested heavily in high-end AI servers to continuously train and optimize their AI models. This reliance on high-end AI servers necessitates the use of high-end AI chips, which in turn will not only drive up demand for HBM during 2023~2024, but is also expected to boost growth in advanced packaging capacity by 30~40% in 2024.

TrendForce highlights that to augment the computational efficiency of AI servers and enhance memory transmission bandwidth, leading AI chip makers such as Nvidia, AMD, and Intel have opted to incorporate HBM. Presently, Nvidia's A100 and H100 chips each boast up to 80 GB of HBM2e and HBM3. In its latest integrated CPU and GPU, the Grace Hopper Superchip, Nvidia expanded a single chip's HBM capacity by 20%, hitting a mark of 96 GB. AMD's MI300 also uses HBM3, with the MI300A capacity remaining at 128 GB like its predecessor, while the more advanced MI300X has ramped up to 192 GB, marking a 50% increase. Google is expected to broaden its partnership with Broadcom in late 2023 to produce the AISC AI accelerator chip TPU, which will also incorporate HBM memory, in order to extend AI infrastructure.

Intel and the German federal government have signed a revised letter of intent for Intel's planned leading-edge wafer fabrication site in Magdeburg, the capital of Saxony-Anhalt state in Germany. The agreement encompasses Intel's expanded investment in the site, now expected to be more than 30 billion euros for two first-of-a-kind semiconductor facilities (also known as "fabs") in Europe, along with increased government support that includes incentives, reflecting the expanded scope and change in economic conditions since the site was first announced.

Intel acquired the land for the project in November 2022, and the first facility is expected to enter production in four to five years following the European Commission's approval of the incentive package. Given the current timeline and scale of the investment, Intel plans to deploy more advanced Angstrom-era technology in the facilities than originally envisioned. The Magdeburg site will serve Intel products and Intel Foundry Services customers.

Global semiconductor materials market revenue grew 8.9% to $72.7 billion in 2022, surpassing the previous market high of $66.8 billion set in 2021, SEMI, the global industry association representing the electronics manufacturing and design supply chain, reported today in its Materials Market Data Subscription (MMDS). Wafer fabrication materials and packaging materials revenue in 2022 reached $44.7 billion and $28.0 billion, respectively, increasing 10.5% and 6.3%. The silicon, electronic gases, and photomask segments showed the strongest growth in the wafer fabrication materials market, while the organic substrates segment largely drove packaging materials market growth.

For the 13th consecutive year, Taiwan, at $20.1 billion, was the world's largest consumer of semiconductor materials on the strength of its foundry capacity and advanced packaging base. China continued to register strong year-over-year results, ranking second in 2022, while Korea finished as the third largest consumer of semiconductor materials. Most regions registered high single- or double-digit growth last year.

MIT researchers have developed a groundbreaking technology that allows for the growth of 2D transition metal dichalcogenide (TMD) materials directly on fully fabricated silicon chips, enabling denser integrations. Conventional methods require temperatures of about 600°C, which can damage silicon transistors and circuits as they break down above 400°C. The MIT team overcame this challenge by creating a low-temperature growth process that preserves the chip's integrity, allowing 2D semiconductor transistors to be directly integrated on top of standard silicon circuits. The new approach grows a smooth, highly uniform layer across an entire 8-inch wafer, unlike previous methods that involved growing 2D materials elsewhere before transferring them to a chip or wafer. This process often led to imperfections that negatively impacted device and chip performance.

Additionally, the novel technology can grow a uniform layer of TMD material in less than an hour over 8-inch wafers, a significant improvement from previous methods that required over a day for a single layer. The enhanced speed and uniformity of this technology make it suitable for commercial applications, where 8-inch or larger wafers are essential. The researchers focused on molybdenum disulfide, a flexible, transparent 2D material with powerful electronic and photonic properties ideal for semiconductor transistors. They designed a new furnace for the metal-organic chemical vapor deposition process, which has separate low and high-temperature regions. The silicon wafer is placed in the low-temperature region while vaporized molybdenum and sulfur precursors flow into the furnace. Molybdenum remains in the low-temperature region, while the sulfur precursor decomposes in the high-temperature region before flowing back into the low-temperature region to grow molybdenum disulfide on the wafer surface.

Semiconductors are largely made using silicon, even though there are other types of substrates that can be used as well, such as gallium nitride or silicon carbide. However, most semiconductors today are made using silicon wafers, which in turn means that silicon wafers are a key material in the semiconductor industry. Over the past three years, the cost of silicon wafers have increased in pricing, due to higher demand, as there has been a higher demand for semiconductors. However, as there are a limited number of suppliers of silicon wafers, especially at the larger 12-inch size, the increased cost in materials has had an impact on the cost of the final semiconductors.

Reports out of Taiwan are suggesting that the price of 12-, 8- and 6-inch wafers are all starting to see a decline in price. We're talking single digit percentages here and it should be noted that these are spot prices, not contract prices, which are negotiated between the parties a long time before delivery. That said, the fact that the spot prices are point downwards also means that companies with not so great contract pricing are starting to want to renegotiate their contract pricing, as even a small saving here can lead to a bigger saving further down the line. Many IC manufacturers have also asked to pause their contract orders, as the utilisation rate of many foundry nodes are going down, which means the foundries aren't in need of as many wafers as they have ordered. Hopefully this will all lead to lower prices across the board when it comes to semiconductors this year, but it's too early to draw any real conclusions. It's also possible that the end customers won't see any direct benefits from lower costs to the manufacturers.

TrendForce's recent analysis of the foundry market reveals that demand continues to slide for all types of mature and advanced nodes. The major IC design houses have cut wafer input for 1Q23 and will likely scale back further for 2Q23. Currently, foundries are expected to maintain a lower-than-ideal level of capacity utilization rate in the first two quarters of this year. Some nodes could experience a steeper demand drop in 2Q23 as there are still no signs of a significant rebound in wafer orders. Looking ahead to the second half of this year, orders will likely pick up for some components that underwent an inventory correction at an earlier time. However, the state of the global economy will remain the largest variable that affect demand, and the recovery of individual foundries' capacity utilization rates will not occur as quickly as expected. Taking these factors into account, TrendForce currently forecasts that global foundry revenue will drop by around 4% YoY for 2023. The projected decline for 2023 is more severe when compared with the one that was recorded for 2019.

United Microelectronics Corporation ("UMC" or "The Company"), a leading global semiconductor foundry, today announced its consolidated operating results for the fourth quarter of 2022. Fourth quarter consolidated revenue was NT$67.84 billion, decreasing 10.0% QoQ from NT$75.39 billion in 3Q22. Compared to a year ago, 4Q22 revenue grew 14.8% YoY from NT$59.10 billion in 4Q21. Consolidated gross margin for 4Q22 was 42.9%. Net income attributable to the shareholders of the parent was NT$19.1 billion, with earnings per ordinary share of NT$1.54.

Jason Wang, co-president of UMC, said, "In the fourth quarter, due to a significant slowdown across most of our end markets and inventory correction in the semiconductor industry, our wafer shipments fell 14.8% QoQ while overall fab utilization rate dropped to 90%. Average selling price increased slightly during the quarter as a result of our ongoing product mix optimization efforts, moderating the decline in revenue."

Cerebras Systems, the pioneer in accelerating artificial intelligence (AI) compute, today unveiled Andromeda, a 13.5 million core AI supercomputer, now available and being used for commercial and academic work. Built with a cluster of 16 Cerebras CS-2 systems and leveraging Cerebras MemoryX and SwarmX technologies, Andromeda delivers more than 1 Exaflop of AI compute and 120 Petaflops of dense compute at 16-bit half precision. It is the only AI supercomputer to ever demonstrate near-perfect linear scaling on large language model workloads relying on simple data parallelism alone.

With more than 13.5 million AI-optimized compute cores and fed by 18,176 3rd Gen AMD EPYC processors, Andromeda features more cores than 1,953 Nvidia A100 GPUs and 1.6 times as many cores as the largest supercomputer in the world, Frontier, which has 8.7 million cores. Unlike any known GPU-based cluster, Andromeda delivers near-perfect scaling via simple data parallelism across GPT-class large language models, including GPT-3, GPT-J and GPT-NeoX.