Friday, November 22nd 2024
AMD's Future Ryzen SoCs May Feature New Chip-Stacking Technology
AMD has recently filed a patent revealing plans to implement "multi-chip stacking" in future Ryzen SoCs, as Wccftech reports, quoting a post on X from @coreteks: "New patent from AMD shows how future Zen SoCs could look. Basically a novel packaging design that enables compact chip stacking and interconnection by having them partially overlap, as in this figure. The dotted line is a larger die stacked on top of those smaller ones". The patent details a new approach where smaller chiplets partially overlap with a larger die, creating space for additional components and functions on the same die. This strategy aims to improve the efficiency of the contact area, thus making room for higher core counts, larger caches, and increased memory bandwidth within the same die size. The proposed stacking will reduce the physical distance between components through overlapping chiplets, thus minimizing interconnect latency and achieving faster communication between different chip parts. The design will also improve power management, as the segregated chiplets allow for better control of each unit through power gating.
Even if long-time rival Intel has lost some of its momentum (and market share) this year, AMD's chance to push ahead with its intention to become number one in the market is to continue to innovate. In the same way that its 3D V-Cache technology made the X3D processor lineup so successful, this chip stacking approach could play a major role in future AMD Ryzen SoCs. It seems that AMD is committed to moving away from the monolithic design era and taking the road of multi-chiplet; however, it can be a long wait until (and if) this chip stacking will complete the journey from patents to design, production, and final product.
Sources:
Wccftech, @coreteks
Even if long-time rival Intel has lost some of its momentum (and market share) this year, AMD's chance to push ahead with its intention to become number one in the market is to continue to innovate. In the same way that its 3D V-Cache technology made the X3D processor lineup so successful, this chip stacking approach could play a major role in future AMD Ryzen SoCs. It seems that AMD is committed to moving away from the monolithic design era and taking the road of multi-chiplet; however, it can be a long wait until (and if) this chip stacking will complete the journey from patents to design, production, and final product.
38 Comments on AMD's Future Ryzen SoCs May Feature New Chip-Stacking Technology
I would also wonder if it means things like NPUs/Accelerators could be interchanged to maximise the product stack across the differing markets. So you could have for example one part with 6 CCDs and 2 Accelerators and another with 2 CCDs and 6 accelerators and everything in between. With AMD moving to chiplet design in GPU as well, perhaps that could be a third option for those stacks.
ROCm needs to be AMDs focus in the short to mid term software wise to start taking some market share from nVidia and to make their CPUs have a real USP over an equivalent Intel.
The one big problem with chiplets was that the interconnects had latency issues and consumed a lot of power, which is why high-end chiplet RDNA3 GPUs did not perform well, to the point that the RDNA4 equivalents have been cancelled. This seeks to improve on those.
What all that in mind, this may not help a lot for CPUs, but it can be one hell of a huge step for GPUs and APUs.... in 2026-7.
Maybe doted line chip is backside
"AMD's Future Ryzen SoC's May Feature New Chip-Stacking Technology"
Wow so future stuff might use new tech??!!? unheard off, usually future stuff uses old tech.....
Remove the word "future" and you just add confusion.
A bait would be: "AMD's insane new chip-stacking - Intel is doomed*?"
*
Give Nomad a break ffs
same happened to hbm
The way I interpreted this news post is that they'll be using something like CoWoS to essentially "bond" the chiplets together through an interposer which will essentially serve the purpose of interconnect, achieving monolithic-like access speeds across chiplets or very close to it, somewhat like an immensely high bandwidth ring bus?
This should be pretty interesting.
But whether this type of products are profitable is up to debate.