Friday, January 17th 2025
AMD to Build Zen 6 CCD on TSMC 3nm Process, Next-Gen cIOD and sIOD on 4nm
AMD is rumored to be building its next-generation CCD (core complex die) that implements the "Zen 6" microarchitecture, on the 3 nm TSMC N3E foundry node. This is part of a set of rumors from ChipHell forum, which got past rumors on AMD right. Apparently, AMD will also refresh the I/O dies for its next generation process, building them on the 4 nm foundry node, likely the TSMC N4C. The TSMC N3E node offers a 20% speed improvement, over 30% power savings, and approximately 60% logic density increase over TSMC N5, whereas the TSMC N4P node that the company uses for its current "Zen 5" chiplets only clock minor increases in logic density and power over N5. The N3E node relies on EUV double-patterning to achieve its logic density increases.
Perhaps the most interesting piece of news is the new-generation I/O dies. AMD is building these on the 4 nm node, which is a significant step up from the 6 nm node its current I/O dies are built on. On the client side of things, 4 nm will enable AMD to give the new cIOD an updated iGPU, probably based on a newer graphics architecture, such as RDNA 3.5. It will also give AMD the opportunity to integrate an NPU. The company might also update its key I/O components, such as the DDR5 memory controllers, to support higher memory speeds unlocked by CUDIMMs. We don't predict any updates on the PCIe front, since AMD is expected to carry on with Socket AM5, which determines that the cIOD puts out 28 PCIe Gen 5 lanes. At best, the USB interface put out from the processor could be updated to USB4 through an on-die host controller. Over on the server side, the new-generation sIOD will bring much needed increases to the DDR5 memory speeds enabled by clock drivers.
The rumor mill also churns out something on graphics. Depending on how the Radeon RX 9000 series and RDNA 4 fare in the market, AMD could revisit the enthusiast segment with its next generation UDNA architecture that the company will make common to both graphics and compute. The company's next-generation discrete GPUs will be built around the TSMC N3E foundry node.
Source:
HXL (Twitter)
Perhaps the most interesting piece of news is the new-generation I/O dies. AMD is building these on the 4 nm node, which is a significant step up from the 6 nm node its current I/O dies are built on. On the client side of things, 4 nm will enable AMD to give the new cIOD an updated iGPU, probably based on a newer graphics architecture, such as RDNA 3.5. It will also give AMD the opportunity to integrate an NPU. The company might also update its key I/O components, such as the DDR5 memory controllers, to support higher memory speeds unlocked by CUDIMMs. We don't predict any updates on the PCIe front, since AMD is expected to carry on with Socket AM5, which determines that the cIOD puts out 28 PCIe Gen 5 lanes. At best, the USB interface put out from the processor could be updated to USB4 through an on-die host controller. Over on the server side, the new-generation sIOD will bring much needed increases to the DDR5 memory speeds enabled by clock drivers.
42 Comments on AMD to Build Zen 6 CCD on TSMC 3nm Process, Next-Gen cIOD and sIOD on 4nm
If you think about it, Strix Halo has an IOD made exclusively for it. I think AM5 has a bigger market, so it doesn't seem that weird to put some effort on it.
Also, why do we want PCI-X in 2025?
Cant be that hard..
What you do need though are retimers/redrivers to ensure signal integrity, if that was what you were thinking of.
Those add a few bucks and we can't get away from those, unless we fundamentally change the motherboard design and stick the CPU in the middle of the motherboard, but even that won't solve the problem entirely.
x8x8x0 or x8x4x4 is common bifurcation operation, but your "fixed" operation wouldn't cost any less than how it's done today, where you can control if you want to use bifurcation or not, since that's a software/firmware feature.
So in other words, what you're asking for, is largely how it works, except the interface speed between the chipset and CPU.
In fact, some expensive motherboards does exactly what you're asking for with regards to the M.2 drives too.
It use way less power and is also in sync with the memory speed. They say a Single CCD can use the full 256 bit bandwidth so that is a great increase over the current infinity fabrics. They say it's also lower latency but we need to considerate that LPDDR memory is higher latency than DDR.
If AMD go that way for Zen Desktop, that would be a big gain for Zen 6 because they would remove a lot of bottleneck of the current architecture.
Apparently MSI have a high end X870 ITX board coming out later this year (Q2 I believe). Just how high end is yet to be seen.
There were also rumours that AMD will experiment with 3d stacking on the I/O die. Either put extra memory on top of it to make the iGPU more powerful (think Strix Halo with crapton of cache), or even put the compute chiplets on top of the I/O for significantly reduced latency and power usage.