Name | Chip | Memory | Shaders | TMUs | ROPs | GPU Clock | Memory Clock |
---|---|---|---|---|---|---|---|
Crayola 6 | 512 MB | 240 | 16 | 8 | 500 MHz | 700 MHz |
48 floating-point vector processors for shader execution, divided in three dynamically scheduled SIMD groups of 16 processors each. Unified shading architecture (each pipeline is capable of running either pixel or vertex shaders) 10 FP ops per vector processor per cycle (5 fused multiply-add) Peak vertex count: 6.0 GVertices/s ((48 shader vector processors × 2 ops per cycle × 500 MHz) / 8 vector ops per vertex) for simple transformed and lit polygons Peak polygon count: 500 million triangles per second Peak shader operations: 96.0 billion shader operations/s (3 shader pipelines × 16 processors × 4 ALUs × 500 MHz) Floating Point Operations: 240.0 GFLOPS (3 shader pipelines × 16 processors × 500 MHz) MEMEXPORT shader function 16 texture filtering units 16 texture addressing units 16 filtered samples per clock Peak texel fillrate: 8.0 GTexel/s (16 textures × 500 MHz) 16 unfiltered texture samples per clock (16 texture addressing units) 8 Render Output units / pixel rendering pipelines Peak pixel fillrate: 4.0 GPixel/s without MSAA (8 ROPs × 500 MHz) Peak Z sample rate: 8.0 GSamples/s (2 Z samples × 8 ROPs × 500 MHz) 32.0 GSamples/s using 4X anti aliasing (2 Z samples × 8 ROPs × 4X AA × 500 MHz) Peak anti-aliasing sample rate: 16.0 GSamples/s (4 AA samples × 8 ROPs × 500 MHz) Peak Dot product operations: 24 billion per second Support for a superset of DirectX Xbox 360 10 MiB daughter embedded DRAM (at 256GB/s) framebuffer on NEC designed eDRAM die includes additional logic 105 million transistors (192 parallel pixel processors) for color, alpha compositing, Z/stencil buffering, and anti-aliasing called “Intelligent Memory”, giving developers 4-sample anti-aliasing at very little performance cost. |