Today, ASML Holding NV (ASML) has published its 2025 first-quarter results.

• Q1 total net sales of €7.7 billion, gross margin of 54.0%, net income of €2.4 billion
• Quarterly net bookings in Q1 of €3.9 billion f which €1.2 billion is EUV
• ASML expects Q2 2025 total net sales between €7.2 billion and €7.7 billion, and a gross margin between 50% and 53%
• ASML continues to expect 2025 total net sales to be between €30 billion and €35 billion, with a gross margin between 51% and 53%

CEO statement and outlook
"Our first-quarter total net sales came in at €7.7 billion, in line with our guidance. The gross margin was 54.0%, above guidance, driven by a favorable EUV product mix and the achievement of performance milestones. In the first quarter, we shipped our fifth High NA system, and we now have these systems at three customers. Our conversations so far with customers support our expectation that 2025 and 2026 will be growth years. However, the recent tariff announcements have increased uncertainty in the macro environment and the situation will remain dynamic for a while. As previously shared, artificial intelligence continues to be the primary growth driver in our industry. It has created a shift in the market dynamics that benefits some customers more than others, contributing to both upside potential and downside risks as reflected in our 2025 revenue range.

High‑NA EUV lithography comes with a crazy $380 million price tag, but it can actually cut overall production costs in the right situations. At the SPIE Advanced Lithography and Patterning conference in February 2025, IBM researchers in Veldhoven revealed that one high‑NA exposure runs about 2.5x the cost of a standard low‑NA shot. That seems steep, yet High‑NA's real strength shows up when it replaces complicated multi‑patterning processes. SemiAnalysis had predicted last year that High‑NA would not become cost‑effective until around 2030, largely because higher dose requirements slow down throughput on the trickiest layers. However, after reviewing IBM's new data, the firm adjusted its outlook. Their model confirms that sticking with Low‑NA double patterning for two-mask sequences remains the cheapest path.

On the other hand, once you need three or more Low‑NA masks, switching to a single High‑NA pass starts to pay off. In fact, for a four‑mask self‑aligned litho‑etch flow, High‑NA can reduce total wafer cost by roughly 1.7-2.1x compared to using Low‑NA multi‑patterning. One big reason fabs are interested is that fewer exposures mean simpler process flows. You cut down cycle time and lower the chance of overlay mistakes. Still, SemiAnalysis warns that a simpler flow does not automatically mean lower expense in every case. Looking at Intel 14A, it turns out only a few critical metal layers at the 14A node hit the sweet spot where High‑NA's higher per‑shot cost is outweighed by ditching multiple masks.

Yesterday, United States President Donald Trump announced a set of tariffs imposed on US trading partners, imposing a series of 10%+ tariffs on partners, calling it a "Liberation Day." Today, we are calculating how much these tariffs will impact consumers and what is most important at TechPowerUp: semiconductors powering our GPUs and CPUs. According to one of the top investment banks, Goldman Sachs, semiconductors are exempt from the reciprocal tariffs that Trump has imposed on Taiwan. However, the semiconductor manufacturing equipment used by makers like TSMC is not exempt and is expected to be hit with the 32% tariffs. This is only half of what Taiwan imposes on imports of US-made goods. For TSMC, the number one maker of GPUs and CPUs, tariffs can be tricky to navigate. While its existing manufacturing facilities use equipment sourced from Dutch ASML and a few US companies like Lam Research and KLA Corporation, it shouldn't be a problem to ship new silicon to the US.

However, if TSMC wants to expand its manufacturing facilities in any country that is not the US, it will have to deal with 32% tariffs on US-sourced silicon manufacturing equipment. For EU-based ASML, things are looking a little different. If over 20% of the equipment is made up of US content, a tariff exemption might apply, potentially reducing import costs. If more than one-fifth of a product's components or value originates from US sources, the equipment may be eligible for tariff relief. ASML's machines include some US components, so determining whether these machines meet the 20% threshold is crucial. If they do, the tariff exemption could help lower costs associated with importing these advanced machines, reaching up to $380 million. For non-US-injected goods, EU entities are subject to 20% tariffs.

According to a report produced by semiconductor industry analysts at Kiwoom Securities—a South Korean financial services firm—Semiconductor Manufacturing International Corporation (SMIC) is expected to complete the development of a 5 nm process at some point in 2025. Jukanlosreve summarized this projection in a recent social media post. SMIC is often considered to be China's flagship foundry business; the partially state-owned organization seems to heavily involved in the production of (rumored) next-gen Huawei Ascend 910 AI accelerators. SMIC foundry employees have reportedly struggled to break beyond a 7 nm manufacturing barrier, due to lack of readily accessible cutting-edge EUV equipment. As covered on TechPowerUp last month, leading lights within China's semiconductor industry are (allegedly) developing lithography solutions for cutting-edge 5 nm and 3 nm wafer production.

Huawei is reportedly evaluating an in-house developed laser-induced discharge plasma (LDP)-based machine, but finalized equipment will not be ready until 2026—at least for mass production purposes. Jukanlosreve's short interpretation of Kiwoom's report reads as follows: (SMIC) achieved mass production of the 7 nm (N+2) process without EUV and completed the development of the 5 nm process to support the mass production of the Huawei Ascend 910C. The cost of SMIC's 5 nm process is 40-50% higher than TSMC's, and its yield is roughly one-third." The nation's foundries are reliant on older ASML equipment, thus are unable to produce products that can compete with the advanced (volume and quality) output of "global" TSMC and Samsung chip manufacturing facilities. The fresh unveiling of SiCarrier's Color Mountain series has signalled a promising new era for China's foundry industry.

TSMC is reconfiguring its US strategy after a challenging start at its Fab 21 facility near Phoenix, Arizona. The company's initial module took nearly five years to move from groundbreaking to production—far longer than the typical two-year process observed in Taiwan. Early setbacks, including labor issues, rising costs, and cultural differences, slowed progress, but these hurdles have provided valuable lessons. With a clearer understanding of the local construction environment, TSMC plans to speed up future projects. Company executives have identified reliable local contractors and addressed many bottlenecks that once hindered progress. As a result, the Taiwanese maker is gearing up to accelerate construction timelines for its upcoming modules. Notably, TSMC intends to start building its third fab—Fab 21 module 3—this year, aiming for a pace similar to that in Taiwan.

In the current phase, TSMC is finalizing equipment installations for Fab 21 module 1 while laying the groundwork for module 2. The plan is to begin trial production of advanced 3 nm-class chips at module 2 in 2026, with high-volume manufacturing expected to kick off by 2028. The accelerated schedule for module 3 is seen as a pathway to faster production of next-generation chips, including those using the N2-series and A16 process technologies. However, rapid construction is not without risks. A critical concern remains the timely procurement of essential fab tools. Leading suppliers such as ASML and Applied Materials face significant backlogs and capacity constraints, which may delay the delivery of necessary equipment. As TSMC vows to build its US capacity more swiftly, the entire supply chain is watching closely to see if these supply chain challenges can be resolved, ensuring that the company meets its ambitious production timelines while expanding its foothold in the American market.

A recent study by TechInsights is reshaping the narrative around the cost of semiconductor manufacturing in the United States. According to the survey, processing a 300 mm wafer at TSMC's Fab 21 in Phoenix, Arizona, is only about 10% more expensive than similar operations in Taiwan. This insight challenges earlier assumptions based on TSMC founder Morris Chang's comments, which suggested that high fab-building expenses in Arizona made US chip production financially impractical. G. Dan Hutcheson of TechInsights highlighted that the observed cost difference largely reflects the expenses associated with establishing a brand-new facility. "It costs TSMC less than 10% more to process a 300 mm wafer in Arizona than the same wafer made in Taiwan," he explained. The initial higher costs stem from constructing a fab in an unfamiliar market with a new, sometimes unskilled workforce—a scenario not typical for mature manufacturing sites.

A significant portion of the wafer production cost is driven by equipment, which accounts for well over two-thirds of the total expenses. Leading equipment providers like ASML, Applied Materials, and Lam Research charge similar prices globally, effectively neutralizing geographic disparities. Although US labor costs are higher than in Taiwan, the heavy automation in modern fabs means that labor represents less than 2% of the overall cost. Additional logistics for Fab 21, including the return of wafers to Taiwan for dicing, testing, and packaging, add complexity but only minimally affect the overall expense. With plans to expand domestic packaging capabilities, TSMC's approach is proving to be strategically sound. This fresh perspective suggests that the apparent high cost of US fab construction has been exaggerated. TSMC's $100B investment in American semiconductor manufacturing reflects a calculated decision informed by detailed cost analysis—demonstrating that location-based differences become less significant when the equipment dominates expenses.

ASML Holding N.V. (ASML) and imec, a leading research and innovation hub in nanoelectronics and digital technologies, today announce that they have signed a new strategic partnership agreement, focusing on research and sustainability. The agreement has a duration of five years and aims to deliver valuable solutions in two areas by bringing together ASML's and imec's respective knowledge and expertise. First, to develop solutions that advance the semiconductor industry and second, to develop initiatives focused on sustainable innovation.

The collaboration incorporates ASML's whole product portfolio, with a focus on developing high-end nodes, using ASML systems including 0.55 NA EUV, 0.33 NA EUV, DUV immersion, YieldStar optical metrology and HMI single- and multi-beam technologies. These tools will be installed in imec's state-of-the-art pilot line and incorporated in the EU- and Flemish-funded NanoIC pilot line, providing the most advanced infrastructure for sub-2 nm R&D to the international semiconductor ecosystem. Focus areas for R&D will also include silicon photonics, memory and advanced packaging, offering full stack innovation for future semiconductor-based AI applications in diverse markets.

China's domestic extreme ultraviolet (EUV) lithography development is far from a distant dream. The newest system, now undergoing testing at Huawei's Dongguan facility, leverages laser-induced discharge plasma (LDP) technology, representing a potentially disruptive approach to EUV light generation. The system is scheduled for trial production in Q3 2025, with mass manufacturing targeted for 2026, potentially positioning China to break ASML's technical monopoly in advanced lithography. The LDP approach employed in the Chinese system generates 13.5 nm EUV radiation by vaporizing tin between electrodes and converting it to plasma via high-voltage discharge, where electron-ion collisions produce the required wavelength. This methodology offers several technical advantages over ASML's laser-produced plasma (LPP) technique, including simplified architecture, reduced footprint, improved energy efficiency, and potentially lower production costs.

The LPP method relies on high-energy lasers and complex FPGA-based real-time control electronics to achieve the same result. While ASML has refined its LPP-based systems over decades, the inherent efficiency advantages of the LDP approach could accelerate China's catch-up timeline in this critical semiconductor manufacturing technology. When the US imposed sanctions on EUV shipments to Chinese companies, the Chinese semiconductor development was basically limited as standard deep ultraviolet (DUV) wave lithography systems utilize 248 nm (KrF) and 193 nm (ArF) wavelengths for semiconductor patterning, with 193 nm immersion technology representing the most advanced pre-EUV production technique. These longer wavelengths contrast with EUV's 13.5 nm radiation, requiring multiple patterning techniques to achieve advanced nodes.

Intel has successfully deployed two advanced ASML High-NA Twinscan EXE:5000 EUV lithography systems at its D1 development facility near Hillsboro, Oregon, processing approximately 30,000 wafers in a single quarter. The High-NA EUV systems, each reportedly valued at $380 million, represent a substantial improvement over previous lithography tools, achieving resolution down to 8 nm with a single exposure compared to the 13.5 nm resolution of current Low-NA systems. Early operational data indicates these machines are approximately twice as reliable as previous EUV generations, addressing reliability challenges that previously hampered Intel's manufacturing progress. The ability to accomplish with a single exposure what previously required three exposures and approximately 40 processing steps has been reduced to just "single digit" processing steps.

Intel has historically been an early adopter of high-NA EUV lithography, a much more aggressive strategy than its competitors like TSMC, which manufactures its advanced silicon using low-NA EUV tools. The company plans to utilize these systems for its upcoming 14A chip manufacturing process, though no specific mass production date has been announced. While ASML classifies these Twinscan EXE:5000 systems as pre-production tools not designed for high-volume manufacturing, Intel's extensive wafer processing is more of a test bed. The early adoption provides Intel with valuable development opportunities across various High-NA EUV manufacturing aspects, including photomask glass, pellicles, and specialized chemicals that could establish future industry standards. Intel's current 18A node is utilizing Low-NA lithography tools, where Intel is only exploring High-NA with it for testing, before moving on to 14A high-volume manufacturing with High-NA EUV.

China's dominance in semiconductor equipment procurement is expected to face its first setback since 2021, with spending projected to decrease from $41 billion to $38 billion in 2025, according to semiconductor research firm TechInsights. This 6% decline marks a significant shift for the world's largest buyer of wafer fabrication equipment, whose purchases represented 40% of global sales in 2024. The downturn reflects mounting pressures from both market dynamics and geopolitical constraints. US export controls targeting advanced semiconductor capabilities have intensified while domestic chipmakers grapple with overcapacity in mature node segments. SMIC, China's leading foundry, has already signaled concerns about oversupply risks in this sector, where Chinese manufacturers have rapidly expanded their market share against Taiwanese competitors.

Despite these headwinds, Chinese equipment manufacturers have notably advanced domestic capability development. Naura Technology Group has emerged as the seventh-largest global equipment manufacturer, while AMEC continues to expand its international presence. However, critical gaps persist in China's semiconductor equipment ecosystem, particularly in lithography systems, where dependence on foreign suppliers like ASML remains high. TechInsights data reveals that Chinese companies supplied only 17% of testing tools and 10% of domestic assembly equipment in 2023. The spending reduction comes after a period of aggressive stockpiling prompted by US sanctions to limit Beijing's access to advanced chipmaking capabilities, especially those applicable to artificial intelligence and military applications. However, Chinese manufacturers have demonstrated resilience, with SMIC and Huawei successfully producing advanced chips through alternative, albeit more costly, manufacturing methods.

Japan's Nikkan Kogyo Shimbun newspaper believes that Rapidus will be installing a grand total of ten "extreme ultraviolet (EUV) exposure tools" at two cutting-edge semiconductor production sites. Government subsidies have assisted in boosting Japan's semiconductor industry to new highs—Rapidus is reportedly catching up with the likes of TSMC. Its 2 nm-class process node could be up and running by 2027, at the currently under-construction Innovative Integration for Manufacturing One (IIM-1) facility. This location welcomed its first ASML NXE:3800E EUV lithography machine last December—this occasion marked the debut deployment of said technology in Japan.

The Nikkan Kogyo Shimbun report cites statements made by Rapidus CEO, Atsuyoshi Koike—according to the boss, ten new machines will be distributed across two fabrication facilities: at the aforementioned IIM-1, as well as IIM-2. The second location is expected to come online not long after the completion of IIM-1. It is not clear whether the foundries will be installing more examples of ASML's NXE:3800E model, and an exact timeframe was not disclosed. An older Nikkei article suggests that a trial run—utilizing 2 nm generation gate-all-around (GAA) technology—will begin around April (2025) at the primary Rapidus fab. A theorized schedule proposes that initial samples are due for shipment to Broadcom (in the USA) by mid-year.

The DeepSeek open-source large language model from China has been the hottest topic in the AI industry over the weekend. The model promises a leap in performance over OpenAI and Meta, and can be accelerated by far less complex hardware. The AI enthusiast community has been able to get it to run on much less complex accelerators such as the M4 SoCs of Mac minis, and gaming GPUs. The model could cause companies to reassess their AI strategy completely, perhaps pulling them away from big cloud companies, toward local acceleration on cheaper hardware; and cloud companies themselves would want to reconsider their orders of AI GPUs in the short-to-medium term.

All this puts the supply chain of AI acceleration hardware in a bit of a spot. The NVIDIA stock is down 12 percent in pre-market trading as of this writing. Microsoft and Meta Platforms also faced a cut, shedding over 3% each. Alphabet lost 3% and Apple 1.5%. Microsoft, Meta and Apple are slated to post their quarterly earnings this week. Companies within NVIDIA's supply chain, such as ASML and TSMC, also saw drops, with ASML and ASM International losing 10-14% in European pre-trading.

Yesterday, the Dutch government announced that it had amended its export rules regarding sanctioned semiconductor equipment—this is another adjustment that seems to align policy closer to North American terms. Equipment manufactured by ASML—the nation's crown jewel photolithography system specialist—is included on a list of sanctioned items. According to a Bloomberg New report, the export of the manufacturer's latest advanced measurement and inspection hardware will be affected by new policy. The Dutch trade ministry stated that only a "very limited" number of technologies will be safeguarded—ASML's customers will be required to apply directly for export licenses with the Dutch government (rather than the USA).

The Hague's announcement did not explicitly state that the latest adjustments were made in conjunction with US government policies, but insider sources reckon that some cross-pollination has occurred. Last December, the White House declared a new wave of restrictions—further constricting semiconductor exports to China. According to an article published by a Netherlands-based legal newspaper, the updated licensing requirements will limit the export of advanced equipment that is utilized to discover small defects in wafers, plus systems that enhance measurements after the deposition and etching phases have been completed.

Rapidus Corporation, a manufacturer of advanced logic semiconductors, today announced the delivery and installation of ASML's EUV lithography equipment at its Innovative Integration for Manufacturing (IIM-1) foundry, an advanced semiconductor development and manufacturing fab currently under construction in Chitose, Hokkaido. To commemorate the installation, a ceremony was held at Portom Hall in the New Chitose Airport.

This is a significant milestone for Japan's semiconductor industry, marking the first time that an EUV lithography tool will be used for mass production in the country. In addition to the EUV lithography machinery, Rapidus will install additional complementary advanced semiconductor manufacturing equipment, as well as full automated material handling systems in its IIM-1 foundry to optimize 2 nm generation gate-all-around (GAA) semiconductor manufacturing.

Intel Corporation today announced that Eric Meurice, former president, chief executive officer and chairman of ASML Holding N.V., and Steve Sanghi, chairman and interim chief executive officer of Microchip Technology Inc., have been appointed to Intel's board of directors, effective immediately. Both will serve as independent directors.

"Eric and Steve are highly respected leaders in the semiconductor industry whose deep technical expertise, executive experience and operational rigor make them great additions to the Intel board," said Frank D. Yeary, interim executive chair of the Intel board. "As successful CEOs with proven track records of creating shareholder value, they will bring valuable perspectives to the board as the company delivers on its priorities for customers in Intel Products and Intel Foundry, while driving greater efficiency and improving profitability."

The EUV lithography machine from ASML ordered by Rapidus is expected to arrive in Japan in mid-December, according to information from Nikkei cited by TrendForce. This marks the first deployment of EUV technology in Japan, an important step for the country's semiconductor industry as it seeks to establish itself as a major player. Rapidus is currently building a factory in Chitose, Hokkaido, and plans to start mass production of 2 nm chips in 2027. The company also plans to purchase several EUV devices if the 2-nanometer chip production is successful, and intends to build a second production facility specifically for 1.4 nm chips. To support these operations, ASML will establish a service center in Chitose City.

NVIDIA CEO Jensen Huang hinted at the possibility of outsourcing AI chip production to Rapidus. As of October, construction progress on the Rapidus facility, which began in September 2023, is up to 63% and remains on track. In addition to Rapidus, Micron's Hiroshima plant is scheduled to install EUV equipment in 2025, allowing for mass production in 2026. JASM, a TSMC subsidiary in Japan, plans to integrate EUV lithography with a second wafer plant in 2027 that will have a 6 nm production line.

Today, the Department of Commerce and Natcast, the operator of the National Semiconductor Technology Center (NSTC), announced the expected location for the first CHIPS for America research and development (R&D) flagship facility. The CHIPS for America Extreme Ultraviolet (EUV) Accelerator, an NSTC facility (EUV Accelerator), is expected to operate within NY CREATES' Albany NanoTech Complex in Albany, New York, supported by a proposed federal investment of an estimated $825 million. The EUV Accelerator will focus on advancing state of the art EUV technology and the R&D that relies on it.

As a key part of President Biden's Investing in America agenda, CHIPS for America is driven by the growing need to bolster the U.S. semiconductor supply chain, accelerate U.S. leading-edge R&D, and create good quality jobs around the country. This proposed facility will bring together NSTC members from across the ecosystem to accelerate semiconductor R&D and innovation by providing NSTC members access to technologies, capabilities, and critical resources.

Today, ASML Holding NV (ASML) has published its 2024 third-quarter results.

• Q3 total net sales of €7.5 billion, gross margin of 50.8%, net income of €2.1 billion
• Quarterly net bookings in Q3 of €2.6 billion of which €1.4 billion is EUV
• ASML expects Q4 2024 total net sales between €8.8 billion and €9.2 billion, and a gross margin between 49% and 50%
• ASML expects 2024 total net sales of around €28 billion
• ASML expects 2025 total net sales to be between €30 billion and €35 billion, with a gross margin between 51% and 53%

CEO statement and outlook
"Our third-quarter total net sales came in at €7.5 billion, above our guidance, driven by more DUV and Installed Base Management sales. The gross margin came in at 50.8%, within guidance. While there continue to be strong developments and upside potential in AI, other market segments are taking longer to recover. It now appears the recovery is more gradual than previously expected. This is expected to continue in 2025, which is leading to customer cautiousness. Regarding Logic, the competitive foundry dynamics have resulted in a slower ramp of new nodes at certain customers, leading to several fab push outs and resulting changes in litho demand timing, in particular EUV. In Memory, we see limited capacity additions, with the focus still on technology transitions supporting the HBM and DDR5 AI-related demand."

According to TechNews Taiwan, Intel has made significant progress in implementing ASML's cutting-edge High-NA EUV lithography technology. The company has successfully completed the assembly of its second High-NA "Twinscan EXE" EUV system at its Portland facility, as confirmed by Mark Phillips, Intel's Director of Lithography Hardware. Christophe Fouquet, CEO of ASML, highlighted that the new assembly process allows for direct installation at the customer's site, eliminating the need for disassembly and reassembly, thus saving time and resources. Phillips expressed enthusiasm about the technology, noting that the improvements offered by High-NA EUV machines have surpassed expectations compared to standard EUV systems. Given the massive $380 million price point of these High-NA systems, any savings are valuable in the process.

The rapid progress in installation and implementation of High-NA EUV technology at Intel's facilities positions the company strongly for production transition. With all necessary infrastructure in place and inspections of High-NA EUV masks already underway, Intel aims to have its Intel 14A process in mass production by 2026-2027. As Intel leads in High-NA EUV adoption, other industry giants are following suit. ASML plans to deliver High-NA EUV systems to TSMC by year-end, with rumors suggesting that TSMC's first system will possibly arrive in September. Samsung has also committed to the technology, although recent reports indicate a potential reduction in their procurement plans. Additionally, this development has sparked discussions about the future of photoresist technology, with Phillips suggesting that while Chemically Amplified Resist (CAR) is currently sufficient, future advancements may require metal oxide photoresists. This provides a small insight into Intel's future nodes.

The Netherlands government announced additional export controls on advanced chipmaking equipment on Friday. This decision, which specifically targets ASML's DUV immersion lithography tools, has drawn sharp criticism from Beijing. The new regulations, aligning with similar restrictions imposed by the US last year, will require additional licensing for the export of ASML's 1970i and 1980i models. China's Commerce Ministry swiftly responded to the announcement, expressing dissatisfaction with what it perceives as unwarranted restrictions on trade. In a statement released Sunday, the ministry accused the United States of leveraging its global influence to pressure allies into tightening export controls, describing it as an attempt to maintain "global hegemony" in the semiconductor industry.

The Chinese government urged the Netherlands to reconsider its position, calling for a balance between security concerns and the preservation of mutually beneficial economic ties. Beijing emphasized the importance of safeguarding the "common interests" of businesses in both countries and warned against potential damage to Sino-Dutch cooperation in the semiconductor sector. Dutch Trade Minister Reinette Klever defended the decision, stating it was made "for our safety." However, this move could have significant implications for ASML, which has already faced restrictions on exporting its most advanced systems to China. ASML receives as much as 49% of its revenue from China, meaning that additional export regulations could significantly reduce revenues if licenses aren't approved.

According to a recent report from Nikkei, China has claimed the number one spot as the single highest spender on chipmaking tools. As the data from SEMI highlights, China spent a whopping $25 billion on key semiconductor tools in the first half of 2024, more than the US, Taiwan, and South Korea combined. And the train of acceleration for the Chinese semiconductor industry doesn't seem to be slowing down, as the country is expected to spend more than $50 billion for the entire year 2024. However, this equipment is not precisely leading-edge, as Chinese companies are under Western sanctions and are unable to source advanced EUV lithography tools for making sub-7 nm chips.

Most of the spending is allocated to mature node chipmaking facilities. These so-called "second tier" companies are driving the massive expenditures, and they are plentiful. Nikkei reports that there are at least ten firms that operate with mature nodes like 10/12/16 nm nodes. Being the biggest spender, China is also one of the primary revenue sources for many companies. For the US chipmaking tool companies like Applied Materials, Lam Research, and KLA, Chinese purchases accounted for 32%, 39%, and 44% of their latest quarterly revenue, respectively. Tokyo Electron recorded orders to China accounting for 49.9% of its revenues in June, while the Netherlands giant ASML also attributed 49%. Perhaps even more interesting is the expected outlook for 2025, which shows no signs of slowing down. The Chinese semiconductor industry must establish complete self-sufficiency, and massive capital expenditures are expected to continue.

Samsung Electronics is set to make a significant leap in semiconductor manufacturing technology with the introduction of its first High-NA 0.55 EUV lithography tool. The company plans to install the ASML Twinscan EXE:5000 system at its Hwaseong campus between Q4 2024 and Q1 2025, marking a crucial step in developing next-generation process technologies for logic and DRAM production. This move positions Samsung about a year behind Intel but ahead of rivals TSMC and SK Hynix in adopting High-NA EUV technology. The system is expected to be operational by mid-2025, primarily for research and development purposes. Samsung is not just focusing on the lithography equipment itself but is building a comprehensive ecosystem around High-NA EUV technology.

The company is collaborating with several key partners like Lasertec (developing inspection equipment for High-NA photomasks), JSR (working on advanced photoresists), Tokyo Electron (enhancing etching machines), and Synopsys (shifting to curvilinear patterns on photomasks for improved circuit precision). The High-NA EUV technology promises significant advancements in chip manufacturing. With an 8 nm resolution capability, it could make transistors about 1.7 times smaller and increase transistor density by nearly three times compared to current Low-NA EUV systems. However, the transition to High-NA EUV comes with challenges. The tools are more expensive, costing up to $380 million each, and have a smaller imaging field. Their larger size also requires chipmakers to reconsider fab layouts. Despite these hurdles, Samsung aims for commercial implementation of High-NA EUV by 2027.

Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents patterned structures obtained after exposure with the 0.55NA EUV scanner in the joint ASML-imec High NA EUV Lithography Lab in Veldhoven, the Netherlands. Random logic structures down to 9,5 nm (19 nm pitch), random vias with 30 nm center-to-center distance, 2D features at 22 nm pitch, and a DRAM specific lay out at P32nm were printed after single exposure, using materials and baseline processes that were optimized for High NA EUV by imec and its partners in the framework of imec's Advanced Patterning Program. With these results, imec confirms the readiness of the ecosystem to enable single exposure high-resolution High NA EUV Lithography.

Following the recent opening of the joint ASML-imec High NA EUV Lithography Lab in Veldhoven, the Netherlands, customers now have access to the (TWINSCAN EXE:5000) High NA EUV scanner to develop private High NA EUV use cases leveraging the customer's own design rules and lay outs.

Japanese professor Tsumoru Shintake of the Okinawa Institute of Science and Technology (OIST) has unveiled a revolutionary extreme ultraviolet (EUV) lithography technology that promises to significantly push down semiconductor manufacturing costs. The new technology tackles two previously insurmountable issues in EUV lithography. First, it introduces a streamlined optical projection system using only two mirrors, a dramatic simplification from the conventional six or more. Second, it employs a novel "dual line field" method to efficiently direct EUV light onto the photomask without obstructing the optical path. Prof. Shintake's design offers substantial advantages over current EUV lithography machines. It can operate with smaller EUV light sources, consuming less than one-tenth of the power required by conventional systems. This reduction in energy consumption also reduces operating expenses (OpEx), which are usually high in semiconductor manufacturing facilities.

The simplified two-mirror design also promises improved stability and maintainability. While traditional EUV systems often require over 1 megawatt of power, the OIST model can achieve comparable results with just 100 kilowatts. Despite its simplicity, the system maintains high contrast and reduces mask 3D effects, which is crucial for attaining nanometer-scale precision in semiconductor production. OIST has filed a patent application for this technology, with plans for practical implementation through demonstration experiments. The global EUV lithography market is projected to grow from $8.9 billion in 2024 to $17.4 billion by 2030, when most nodes are expected to use EUV scanners. In contrast, ASML's single EUV scanner can cost up to $380 million without OpEx, which is very high thanks to the power consumption of high-energy light UV light emitters. Regular EUV scanners also lose 40% of the UV light going to the next mirror, with only 1% of the starting light source reaching the silicon wafer. And that is while consuming over one megawatt of power. However, with the proposed low-cost EUV system, more than 10% of the energy makes it to the wafer, and the new system is expected to use less than 100 kilowatts of power while carrying a cost of less than 100 million, a third from ASML's flagship.

Today, ASML Holding NV (ASML) has published its 2024 second-quarter results.

• Q2 total net sales of €6.2 billion, gross margin of 51.5%, net income of €1.6 billion
• Quarterly net bookings in Q2 of €5.6 billion of which €2.5 billion is EUV
• ASML expects Q3 2024 total net sales between €6.7 billion and €7.3 billion and a gross margin between 50% and 51%

CEO statement and outlook
"Our second-quarter total net sales came in at €6.2 billion, at the high-end of our guidance, with a gross margin of 51.5% which is above guidance, both primarily driven by more immersion systems sales. In line with previous quarters, overall semiconductor inventory levels continue to improve, and we also see further improvement in litho tool utilization levels at both Logic and Memory customers. While there are still uncertainties in the market, primarily driven by the macro environment, we expect industry recovery to continue in the second half of the year. We expect third-quarter total net sales between €6.7 billion and €7.3 billion with a gross margin between 50% and 51%. ASML expects R&D costs of around €1,100 million and SG&A costs of around €295 million. Our outlook for the full year 2024 remains unchanged. We see 2024 as a transition year with continued investments in both capacity ramp and technology. We currently see strong developments in AI, driving most of the industry recovery and growth, ahead of other market segments," said ASML President and Chief Executive Officer Christophe Fouquet.