ValantarFrom the looks of it this is two SSDs - a PCIe x2 NVMe Optane Memory module and a PCIe x2 NAND SSD (with DRAM cache, judging by the render!) - on a single board. That's a shame, really, as a solution like this with everything integrated into a single controller with integrated caching algorithms and no DRAM is pretty much the killer app for Optane. The capacities seem just right, so all that's missing is a better controller, and this could be amazing.

holyprofIs it that hard to replace SSD controller RAM buffer with 32GB x-point and have cheap ultra-fast 1TB SSD?

ValantarWell, in a word, yes. You'd need to replace the (small, simple, scalable, low-power, industry-standard, ubiquitous) DDR3/4 controller in the SSD controller with a (large-ish, complex, proprietary, relatively new and untested) 3D Xpoint controller. The picture posted by @TheLostSwede above shows the size of such a controller (in a package, but it's unlikely that the controller is much smaller than the package) - and the DRAM controller portion of the SSD controller is not that large, so you can pretty much just add its area to the SSD controller's area for a ballpark estimate of the resulting chip size, even if that tells us nothing of the complexity of making such a thing (especially integrating tiering/caching logic, which would either require a lot of processing power (=faster, so hotter or bigger cores) or bespoke hardware (=more die area).

So, this is what we would all want (as using RST means you're platform locked and stuck with half the interface speed for your SSD), it'll be a while until we see it - and it won't be cheap when we do.

CrackongSo it is a fast but small SSD replacing the DRAM cache to help a large but handicapped SSD, all in one package ?

holyprofSeems like a pure Optane SSD is a more viable option then (high price, but at least easier to build). Until they are available at reasonable (for a hardware enthusiast or professional) prices, classic high-end SSDs will do.

TheLostSwedeNot quite, the SSD part still has a DRAM cache. The Optane part ends up as a write cache, which means that up to 32GB of data can be written really fast and that is then flushed to the slow QLC SSD at whatever pace the SSD can accept the data. It might also work as a read cache, but it's not clear how much of the Optane memory would be taken up as a read cache, so it might end up being less than 32GB as a write buffer. The QLC SSD still has DRAM though.

londisteI would say physical size is a serious concern here. High-performance SSD is moving to M.2 and primarily 2280. So far, Optane SSDs can only fit 128GB on that. Also, power and cooling.

jabbadapIt's 118GB(well yes technically 128GB), I know sounds arbitrary odd number. And you are spot on, density is the major reason for not getting bigger drives on that form factor.

What are the densities for IMFTs 3D Xpoints anyway(Or micron now-a-days)? I presume Optane 800p uses the highest density chips, it being single sided I presume those two are 64GB chips. Am I right or is there some PoP -chip packaging going on?

londisteWhen it comes to M.2, Intel does have 905P with 380GB (and the data center counterpart DC P4801X):
ark.intel.com/content/www/us/en/ark/products/148607/intel-optane-ssd-905p-series-380gb-m-2-110mm-pcie-x4-20nm-3d-xpoint.html
This has 7 XPoint chips on it so looks like they are only (mass) producing 64GB dies at this time.

CrackongLooks like nobody wants QLC so they had to come up with something to push some sales.

er557They can't enable it on motherboards that dont have the lanes or lack such support, say amd based / budget boards. It might be this device is splitting the controllers INTERNALLY, transparent to the slot, not by using the motherboard for splitting the lanes. But yeah, other solutions are available for intel proprietary features, such as bios modding, efi modding, to enable VROC or bifurcation where applicable.

Scrizzlol, do you really think designing something like this only takes months? lol

ValantarSo you're suggesting this has an onboard PLX chip for PCIe switching? Those are about $100 apiece, so that's not quite likely. "Transparent to the slot" is meaningless - the slot is just a receptacle with wires. What matters is how the chipset or cpu allocates the lanes, and the only way this product works is if each controller on the drive is given two lanes out of the four provided by the interface. Which, again, means that the CPU or chipset is bifurcating what would otherwise be a monolithic x4 interface, which no other device is allowed to do on a consumer Intel platform.

Scrizzlol, do you really think designing something like this only takes months? lol

londisteWhy? Even simple things like M.2 expansion boards are doing 16 > 4x4 quite easily.
PLX chips are switches, this thing doesn't need one.

ValantarWhich, again, means that the CPU or chipset is bifurcating what would otherwise be a monolithic x4 interface, which no other device is allowed to do on a consumer Intel platform.
As for you for some reason mentioning AMD chipsets: while it's embarrassingly obvious that Intel has no power to enable or disable features in those, AMD already supports PCIe bifurcation on their consumer platforms (though from the CPU as they don't provide much PCIe through their chipsets). Go figure.

Scrizzlol, do you really think designing something like this only takes months? lol