Monday, March 30th 2020
DDR5 Arrives at 4800 MT/s Speeds, First SoCs this Year
Cadence, a fabless semiconductor company focusing on the development of IP solutions and IC design and verification tools, today posted an update regarding their development efforts for the 5th generation of DDR memory which is giving us some insights into the development of a new standard. The new DDR5 standard is supposed to bring better speeds and lower voltages while being more power-efficient. In the Cadence's blog called Breakfast Bytes, one of Cadence's memory experts talked about developments of the new standards and how they are developing the IP for the upcoming SoC solutions. Even though JEDEC, a company developing memory standards, hasn't officially published DDR5 standard specifications, Cadence is working closely with them to ensure that they stay on track and be the first on the market to deliver IP for the new standard.
Marc Greenberg, a Cadence expert for memory solutions was sharing his thoughts in the blog about the DDR5 and how it is progressing. Firstly, he notes that DDR5 is going to feature 4800 MT/s speeds at first. The initial speeds will improve throughout the 12 months when the data transfer rate will increase in the same fashion we have seen with previous generation DDR standards. Mr. Greenberg also shared that the goals of DDR5 are to have larger memory dies while managing latency challenges, same speed DRAM core as DDR4 with a higher speed I/O. He also noted that the goal of the new standard is not the bandwidth, but rather capacity - there should be 24Gb of memory per die initially, while later it should go up to 32Gb. That will allow for 256 GB DIMMs, where each byte can be accessed under 100 ns, making for a very responsive system. Mr. Greenberg also added that this is the year of DDR5, as Cadence is receiving a lot of orders for their 7 nm IP which should go in production systems this year.
Sources:
Cadence, AnandTech (Image)
Marc Greenberg, a Cadence expert for memory solutions was sharing his thoughts in the blog about the DDR5 and how it is progressing. Firstly, he notes that DDR5 is going to feature 4800 MT/s speeds at first. The initial speeds will improve throughout the 12 months when the data transfer rate will increase in the same fashion we have seen with previous generation DDR standards. Mr. Greenberg also shared that the goals of DDR5 are to have larger memory dies while managing latency challenges, same speed DRAM core as DDR4 with a higher speed I/O. He also noted that the goal of the new standard is not the bandwidth, but rather capacity - there should be 24Gb of memory per die initially, while later it should go up to 32Gb. That will allow for 256 GB DIMMs, where each byte can be accessed under 100 ns, making for a very responsive system. Mr. Greenberg also added that this is the year of DDR5, as Cadence is receiving a lot of orders for their 7 nm IP which should go in production systems this year.
28 Comments on DDR5 Arrives at 4800 MT/s Speeds, First SoCs this Year
www.thermaltake.com/toughram-memory-ddr4-4400mhz-16gb-8gb-x-2.html
I doubt that anything slower than DDR5-7000 will have any meaning.
Especially with the associated high power consumption.
Notebooks work with DDR4-2400 (very often single channel at that!) and lower power saving clocks in order to keep the thermals in check.
www.techpowerup.com/243907/cadence-and-micron-demo-ddr5-4400-memory-module
DDR3 at CAS11, then DDR4 at CAS14, now you want DDR5 at CAS33 in the best case.
I find now that DDR3 has CAS6, CAS7... CAS9 as well. :eek:
I remember an AData Kit DDR3-1333 CAS11. :(
I'm surprised we don't have a fast decoupler chip on the RAM PCB, but that itself adds complexity, cost, and latency.
Manufacturers have always sold modules that go far beyond spec.
I had DDR3 at CL9 1866
I had DDR4 at CL15 2666
Now I'll have DDR5 at CL22 4400
The clocks keep climbing but so does the latency!
:cool:
DDR2-1066 @ CL5 is ~9.4ns
DDR3-1866 @ CL9 is ~9.6ns
DDR4-2666 @ CL15 is ~11.3ns
DDR5-4400 @ CL22 is 10ns
But the highest value for the preliminary JEDEC DDR5 is 6400MT/s which has already been presented by SK Hynix.
DDR5-6400 @ CL22 is ~6.9ns
DDR5-6400 @ CL32 is 10ns
We don't know the final timings yet either way.
One other thing is the adoption rate. We've only recently been able to use DDR4-3200 officially with Zen 2 and Ice Lake. Intel still doesn't officially support anything faster than DDR4-2933 in Xeons as far as I know. Even Cascade Lake Refresh is capped at that. Therefore DDR5 will take time to ramp up and DDR4 will be superior in performance to the early iterations.But that's not JEDEC-specc. DDR5 in the preliminary specc goes to 6400. How high will it go if you make speedier modules? >9000? :)
JEDEC is free to certify DDR4-4400.
But I'm not sure that AMD is ready to design a memory controller which can support such speeds.
Hopefully, they will investigate the issues with DDR5 and decide whether it's worth it to move on to it.
1. Those speeds came years after JEDEC DDR4 was created.
2. You can't make enough of the highest performance chips.
3. The server market is on a completely different cadence than the consumer market. Everything takes longer there. Nobody will take time to certify a DDR4-4400 memory line just to have it replaced in 2 years. No manufacturer will give you the same guarantees for DDR4-4400 as they do with JEDEC standard ones. The memory types used in servers have a lot of differences from the mainstream (ECC, LRDIMM, RDIMM and so on).Sure, but nobody (in the server market) would use it compared to the older versions of the standard. It's just easier to everybody to move to the next tier which is DDR5.I'm not sure why you think that AMD, a company that has enormous experience in memory, would have any problems with designing a memory controller. They have used various DDRs, GDDRs and even HBM in their own designs. If anything they are the experts in this field :)
The more instructions and data you fetch at once the less likely you are to need more additional access times for data that wasn't found in the cache lines moved. It's all designed very well with a clear purpose in mind, you should learn how these things actually work before you come up with these claims.
Imagine having billion dollar companies come up with designs that are worse and presumably no one noticed except you, come on.
Don't believe me, look at AMD's chiplet design which technically produces abhorrent memory access times compared to equivalent processors yet they even outperform them.
www.tomshardware.com/news/first-native-ddr4-3200-ram-century-micro,39804.htmllol... nothing new dude... nothing at all, move on...
As time goes on, they tighten down and speed up....you are not saying anything most don't know already.
All it brings, especially out of the gate, is lower operating voltage (yipee!). In many home/consumer cases, memory bandwidth isn't a concern in the first place... so... cool, another iteration of memory. :)The problem is that not all memory controllers can handle that speed. JEDEC is a baseline specification designed for compatibility and stability. Your XMP profiles are overclocking the IMC, but not the sticks themselves as they are rated to perform that speed.
I still have 32GB of quad channel DDR3 2133 9-11-10-28 running on my x79 system. I'm putting 128GB DDR4 3600 16-19-19-39 in my TR3 system.
Early adopters pay a high price and a high performance penalty when it comes to RAM. The exception is chips that become 'legendary' like BH5, Micron D9 and Samsung B-die which shot up in cost when people figured them out.