Wednesday, March 17th 2021
DDR5-6400 RAM Benchmarked on Intel Alder Lake Platform, Shows Major Improvement Over DDR4
As the industry is preparing for a shift to the new DDR standard, companies are trying to adopt the new technology and many companies are manufacturing the latest DDR5 memory modules. One of them is Shenzhen Longsys Electronics Co. Ltd, a Chinese manufacturer of memory chips, which has today demonstrated the power of DDR5 technology. Starting with this year, client platforms are expected to make a transition to the new standard, with the data center/server platform following. Using Intel's yet unreleased Alder Lake-S client platform, Longsys has been able to test its DDR5 DIMMs running at an amazing 6400 MHz speed and the company got some very interesting results.
Longsys has demoed a DDR5 module with 32 GB capacity, CAS Latency (CL) of 40 CL, operating voltage of 1.1 V, and memory modules clocked at 6400 MHz. With this being an impressive memory module, this is not the peak of DDR5. According to JEDEC specification, DDR5 will come with up to 8400 MHz speeds and capacities that are up to 128 GB per DIMM. Longsys has run some benchmarks, using an 8-core Alder Lake CPU, in AIDA64 and Ludashi. The company then proceeded to compare these results with DDR4-3200 MHz CL22 memory, which Longsys also manufactures. And the results? In AIDA64 tests, the new DDR5 module is faster anywhere from 12-36%, with the only regression seen in latency, where DDR5 is doubling it. In synthetic Ludashi Master Lu benchmark, the new DDR5 was spotted running 112% faster. Of course, these benchmarks, which you can check out here, are provided by the manufacturer, so you must take them with a grain of salt.
Source:
Longsys
Longsys has demoed a DDR5 module with 32 GB capacity, CAS Latency (CL) of 40 CL, operating voltage of 1.1 V, and memory modules clocked at 6400 MHz. With this being an impressive memory module, this is not the peak of DDR5. According to JEDEC specification, DDR5 will come with up to 8400 MHz speeds and capacities that are up to 128 GB per DIMM. Longsys has run some benchmarks, using an 8-core Alder Lake CPU, in AIDA64 and Ludashi. The company then proceeded to compare these results with DDR4-3200 MHz CL22 memory, which Longsys also manufactures. And the results? In AIDA64 tests, the new DDR5 module is faster anywhere from 12-36%, with the only regression seen in latency, where DDR5 is doubling it. In synthetic Ludashi Master Lu benchmark, the new DDR5 was spotted running 112% faster. Of course, these benchmarks, which you can check out here, are provided by the manufacturer, so you must take them with a grain of salt.
49 Comments on DDR5-6400 RAM Benchmarked on Intel Alder Lake Platform, Shows Major Improvement Over DDR4
DDR4 3200 CL16 is an overclocked memory preset
This is common config of ECC modules. And they are 1,2V (since 1,35 is overclocking).
www.crucial.com/memory/server-ddr4/mta18asf4g72az-3g2b1
Instruct yourself with this and get back after that:
www.micron.com/-/media/client/global/documents/products/white-paper/ddr5_more_than_a_generational_update_wp.pdf?la=en
How do you expect memory to perform with 800MHz CPU clock?
This benchmark if more of a ''Oh hey look DDR5 exists'' rather than a valid performance metric. It's incredibly early for DDR5
And users are still wrong when referencing DDR4 as somehow having quad channel by using 4 sticks instead of two on mainstream platforms (not X299 or TR). That needs to be pointed out.Why would that matter? That 800Mhz would affect system performance not memory performance. Unless the IMC was somehow downlocked or something...
That 800Mhz clock explains everything now = bandwith/memory latency/cache latency
Which means cache frequency was also 800 or lower.
Page 4 of 6The example is for server. So a server that have a motherboard layout for 8 channel, they will be able to keep a similar layout but this time, they will be able to support 16 channel with the same amount of trace and pin.
A motherboard that is routed for dual channel right now, so by example 2 channel of 2 dimm slot, 1 channel per 288 pin, will have 4 channel with DDR5. The 2 288 pin/trace will still lead to 2 DIMM slot, but they will give 2x32 Channel per 288 pin/trace instead of 1x64.
And a schema from that document explain it well
1=9900k 5.0/4.6 / HT OFF
2=9900k 0.8/0.8 / HT OFF
Same Deal with PCI vs PCI-E. There are reason for this.
The wider the bus, the harder it is to move data across over long distance at higher frequency. This is why everyone is looking at smaller serial bus that run much faster.
But as a comparaison, DDR5 6400 will be able to send the same 64B line to the CPU in the same exact amount of time it would take a DDR4-3200 DIMM to do. The only difference it will only use half the dimm to do it. The other channel on the DIMM will be free do to other useful work.
lol everyone posting what is this crap my DDR4 numbers are better than this.
This is par the course it happends at every new memory generation. DDR5 will eventually give better performance but that will take time not at launch.
The Micron whitepaper explain it well in simple word but if you want a more reliable source, this is on the JEDEC web site:
www.jedec.org/news/pressreleases/jedec-publishes-new-ddr5-standard-advancing-next-generation-high-performanceAll DDR5 DIMM that respect the JEDEC standard will have 2 channel on them (where DDR4 and bellow DIMM only have 1 channel).
But there are design change in DDR5 that will improve that actually might not appear in syntethic benchmark. By having 2 memory channel per dimm for a total of 4, you have more memory channel per core. This can mean you can spread your memory read and write to many controller. This make them more available reducing the real latency but maybe not the synthetic one.
Also, unlike DDR4, DDR5 will refresh it's bank on a per bank basis instead of the whole bank group. DRAM still need refreshing and while the memory controller does it, the bank group is unavailable. With DDR5, the rest of the memory will still be able to accomplish some work, reducing again the overall latency but that might not change much the synthetic one
Micron state that at equal spec (So DDR4 3200 vs DDR5-3200), the DDR5 module should be 1.36 time more performant due to all the change they made.
DDR5 is actually a big overhaul of the DDR standard where most of the previous DDR iteration were minor change mixed with doubling the data rate.
Alder Lake needs to have four memory channels because that's the only way it can transfer data over a 128-bit bus to and from RAM. With only two channels, only 64-bit transfers would be possible, cutting the bandwidth in half compared to dual channel DDR4 at same speed rating. Intel can't afford to cut bandwidth in half overnight.
That said, it's quite possible that there will be no more than two independent channels on the IMC, each with its own buffers, queues, reorder logic, possibly some cache and whatnot. Each of these channels will control data flow over two 32-bit buses ("sub-channels"), with same access pattern on both. The whole thing amounts to two channels by 64 bits each and Intel won't even try to sell it as four-channel. They may still introduce an IMC with four independent channels at a later time and market it as such. "A later time" = the other generation on LGA 1700.
Now I've started wondering what the purported "12-channel DDR5" means in AMD Genoa's case. 12 x 32-bit would be a heavy regression from 8 x 64-bit on Zen 3. So 24 channels but only 12 independent channels, hmm?
Except that both channel will have their own command pin and will need to be managed independently by the memory controller. It is not like the memory controller of GPU.
This give way more flexibility on the memory controller chips as it's easier to fit 4 block of 32 bit memory controller than 2 64 bit block.
On the motherboard. Except the voltage controller. There won't be many change and there will be 2 memory domain like the current situation. The trace on the motherboard are also way easier to trace since you only need to katch
For Genoa. AMD will have up to 12 Chiplets per chips. If they respect the memory configuration of the previous EPYC cpu, it would make sense they go with 12 independ physical domain or DIMM channel with 24 subchannel.
The controller can be made simpler if only two channels are independent. The other two just follow the first two, doubling the bandwidth. For large transfers, you get the full bandwidth of a 128-bit bus. But if four threads request data from four different memory locations, only two requests can be processed at a time. It's a tradeoff, and maybe Intel decides it's good enough for Alder Lake's cores.
Phenoms X4 even had a BIOS option to select ganged mode (two DDR2 channels working as one, or 1 x 128 bit) or unganged mode (two independent DDR2 channels, 2 x 64 bit). In benchmarks, unganged was faster in games and equally fast in everything else.
The DDR4 stick cannot be running at 3200 MT/s, as the max theoretical bandwidth at that speed is 25600 GB/s. Actual benchmark results are always a few GB/s slower.
Latency is always really bad in the beginning, so it is not even worth looking at that.
I hope new CPUs and boards will support both standards for a few years. If you have fast XMP DDR4 memory, there is zero point in replacing it with JEDEC-spec DDR5.