Thursday, November 2nd 2023
Intel Itanium Reaches End of the Road with Linux Kernel Stopping Updates
Today marks the end of support for Itanium's IA-64 architecture in the Linux kernel's 6.7 update—a significant milestone in the winding-down saga of Intel Itanium. Itanium, initially Intel's ambitious venture into 64-bit computing, faced challenges and struggled throughout its existence. It was jointly developed by Intel and HP but encountered delays and lacked compatibility with x86 software, a significant obstacle to its adoption. When AMD introduced x86-64 (AMD64) for its Opteron CPUs, which could run x86 software natively, Intel was compelled to update Xeon, based on x86-64 technology, leaving Itanium to fade into the background.
Despite ongoing efforts to sustain Itanium, it no longer received annual CPU product updates, and the last update came in 2017. The removal of IA-64 support in the Linux kernel will have a substantial impact since Linux is an essential operating system for Itanium CPUs. Without ongoing updates, the usability of Itanium servers will inevitably decline, pushing the (few) remaining Itanium users to migrate to alternative solutions, which are most likely looking to modernize their product stack.
Source:
Phoronix
Despite ongoing efforts to sustain Itanium, it no longer received annual CPU product updates, and the last update came in 2017. The removal of IA-64 support in the Linux kernel will have a substantial impact since Linux is an essential operating system for Itanium CPUs. Without ongoing updates, the usability of Itanium servers will inevitably decline, pushing the (few) remaining Itanium users to migrate to alternative solutions, which are most likely looking to modernize their product stack.
33 Comments on Intel Itanium Reaches End of the Road with Linux Kernel Stopping Updates
Note 1:
I worked on a project related to porting a scientific library to Intel Itanium IA-64 Architecture. Unfortunately, the project was cancelled after Intel announced Itanium processors would be discontinued.
Note 2:
There was a question "Who is still running some software on it?". It could be R&D Labs at Universities, Supercomputing Centers, like TACC.
Note 3:
Even older Intel CPUs significantly outperform Intel Itanium CPUs. Here are two sets of Intel CPUs ( Intel Itanium vs. Intel Xeon Phi ) for comparison:
// Intel Itanium Processors - Processing Power
www.intel.com/content/dam/support/us/en/documents/processors/APP-for-Intel-Itanium-Processors.pdf
9010 12.80 GFLOPs
9015 11.20 GFLOPs
9020 11.36 GFLOPs
9030 12.80 GFLOPs
9040 12.80 GFLOPs
9050 12.80 GFLOPs
9110N 12.80 GFLOPs
9120N 11.36 GFLOPs
9130M 13.28 GFLOPs
9140M 13.28 GFLOPs
9140N 12.80 GFLOPs
9150M 13.28 GFLOPs
9150N 12.80 GFLOPs
9152M 13.28 GFLOPs
9310 12.80 GFLOPs
9320 21.33 GFLOPs
9330 23.36 GFLOPs
9340 25.60 GFLOPs
9350 27.68 GFLOPs
9520 27.68 GFLOPs
9540 68.16 GFLOPs
9550 38.40 GFLOPs
9560 80.96 GFLOPs
9720 27.68 GFLOPs
9740 68.16 GFLOPs
9750 40.48 GFLOPs
9760 85.12 GFLOPs
// Intel Xeon Phi Processors - Processing Power
www.intel.com/content/dam/support/us/en/documents/processors/APP-for-Intel-Xeon-Phi-Processors.pdf
7235 1331.00 GFLOPs
7255 1197.00 GFLOPs
7285 1414.00 GFLOPs
7295 1728.00 GFLOPs
7210 2662.00 GFLOPs
7230 2662.00 GFLOPs
7250 3046.00 GFLOPs
7290 3456.00 GFLOPs
7210F 2662.00 GFLOPs
7230F 2662.00 GFLOPs
7250F 3046.00 GFLOPs
7290F 3456.00 GFLOPs
SIMD is nice but you still don't get much of it from high-level or portable programming languages.
No any problems with our source codes. The problem was with hardware because it was Too Expensive and performance was so-so ( see my previous post ).
Here are, for example, outputs from my Software Development Environment for Itanium:
...
Setting environment for using Microsoft Visual Studio 2005 x86 tools.
Targeting Windows Server 2003 IA64 ( Itanium 64-bit ) RETAIL
Intel(R) C++ Compiler Professional for applications running on IA-64, Ver 11.0.075
Copyright (C) 1985-2009 Intel Corporation. All rights reserved.
...
C:\>cl.exe /?
Microsoft (R) C/C++ Optimizing Compiler Version 14.00.40310.39 for IA-64
Copyright (C) Microsoft Corporation. All rights reserved.
...
C:\>icl.exe /?
Intel(R) C++ Compiler Professional for applications running on IA-64, Version 11.0
Build 20090609 Package ID: w_cproc_p_11.0.075
...
And as you say, the problem was not only X86 compatibility(which was utter shit), is that even with native code it was not particularly fast, it was the wrong product at the wrong time.
maybe in a fantastic future where we have AI compilers or runtime AI compilers that change the compilation according to the workflow or some shit like that it "could" work....
and yes, the real tragedy in all this was DEC, Intel should've ditched shitanium and kept developing the ALPHA which was already 64bit and blazing fast and had already known software for a long time, i mean if you're going to ditch x86 might as well go for alpha and maybe develop some kind of hardware emulation/translation layer
...
/O2 optimize for maximum speed (DEFAULT)
...
/Qvec[-] enables(DEFAULT)/disables vectorization
...
OpenMP was the easiest way to enable parallelization ( in our codes almost all for-loops have #pragma omp ... directives ):
...
/Qopenmp enable the compiler to generate multi-threaded code based on the OpenMP* directives
...
Auto-Parallelization was also available (!):
...
/Qparallel enable the auto-parallelizer to generate multi-threaded code for loops that can be safely executed in parallel
...
SIMD-like features for explicit application of vectorization was also available from fvec.h and dvec.h:
...
const union
{
int i[4];
__m128d m;
} __f64vec2_abs_mask_cheat = {0xffffffff, 0x7fffffff, 0xffffffff, 0x7fffffff};
#define _f64vec2_abs_mask ((F64vec2)__f64vec2_abs_mask_cheat.m)
/* EMM Functionality Intrinsics */
class I8vec16; /* 16 elements, each element a signed or unsigned char data type */
class Is8vec16; /* 16 elements, each element a signed char data type */
class Iu8vec16; /* 16 elements, each element an unsigned char data type */
class I16vec8; /* 8 elements, each element a signed or unsigned short */
class Is16vec8; /* 8 elements, each element a signed short */
class Iu16vec8; /* 8 elements, each element an unsigned short */
class I32vec4; /* 4 elements, each element a signed or unsigned long */
class Is32vec4; /* 4 elements, each element a signed long */
class Iu32vec4; /* 4 elements, each element a unsigned long */
class I64vec2; /* 2 element, each a __m64 data type */
class I128vec1; /* 1 element, a __m128i data type */
...