Monday, August 19th 2024
Intel Readies Core Ultra 3 205, Brings E-cores to the "3" Tier
Intel may have debuted its Hybrid (heterogeneous multicore) architecture for the desktop with the 12th Gen Core "Alder Lake-S," but the value-ended Core i3 series SKUs throughout the 12th, 13th, and 14th Gen Core processors have remained 4-core/8-thread traditional multicore chips, with just four P-cores. Intel is about to change this with the Core Ultra 200 series "Arrow Lake-S." According to OneRaichu, a reliable source with Intel leaks, the company is giving finishing touches to a pair of Core Ultra 3 series desktop processor SKUs based on the "Arrow Lake" microarchitecture. These will be 8-core chips, a doubling in core-count form the past generations, but the nature of these 8 cores is not yet known.
Among the SKUs in the leak are the Core Ultra 3 205, and the Core Ultra 3 215, both of which are 8-core chips. The two are probably differentiated in a similar manner to past generations of Intel Core i3 desktop did, using cache sizes (eg: Core i3-10100 and i3-10300). The chips probably feature a 4P+4E core configuration, as a "2P+6E" configuration might not be possible, as the E-core clusters are indivisible, although we don't know if the same rule applies to the "Skymont" E-core clusters. The dedicated L2 caches of both the P-cores and E-core clusters could be smaller than on Core Ultra 5 and above SKUs. The Core Ultra 200V "Lunar Lake" processor uses "Lion Cove" P-cores with 2.5 MB of L2 cache per core, while the Core Ultra 9 285K probably has "Lion Cove" P-cores with 3 MB of L2 cache per core.
Sources:
OneRaichu (Twitter), PCGamesN
Among the SKUs in the leak are the Core Ultra 3 205, and the Core Ultra 3 215, both of which are 8-core chips. The two are probably differentiated in a similar manner to past generations of Intel Core i3 desktop did, using cache sizes (eg: Core i3-10100 and i3-10300). The chips probably feature a 4P+4E core configuration, as a "2P+6E" configuration might not be possible, as the E-core clusters are indivisible, although we don't know if the same rule applies to the "Skymont" E-core clusters. The dedicated L2 caches of both the P-cores and E-core clusters could be smaller than on Core Ultra 5 and above SKUs. The Core Ultra 200V "Lunar Lake" processor uses "Lion Cove" P-cores with 2.5 MB of L2 cache per core, while the Core Ultra 9 285K probably has "Lion Cove" P-cores with 3 MB of L2 cache per core.
24 Comments on Intel Readies Core Ultra 3 205, Brings E-cores to the "3" Tier
So this move make sense to me. With 8 cores, you still have those 8 threads former i3 had.
My guess will be a 4p + 4e core configuration. 2p cores seems to little and 6p + 2e cores is to good to be true knowing intel.
Using Windows on a N100 with 4 physical E cores is better than an older I3 or older I5 that is 2 cores with HT.
It is possible such a CPU could exist but, like I said, never under the "Intel Core" brand.
I think it will be interesting to compare Raptor Cove cores to Lion Cove cores as you can generally disable the E-cores in the bios and see how a new arch without HT goes against the old arch with HT. I suspect it won't make as much of a difference as people expect.
Core Ultra 3
Core Ultra 5
Core Ultra 7
Super Ultra
Ultra Boy
Captain Ultra
Tide Ultra Oxi
and finally
Dawn Ultra Platinum Advance Power! AMD 7800X3D can eat it's grease fighting powers dust!
it´s ram is doing some magical things because it never gets full it seems...
I don't know if memory management can be called magic outside Clarke's third law. :D
Chrome OS uses a technique called zRAM to compress infrequently used data in memory.
This effectively creates more free space, allowing more tabs and apps to remain active without causing slowdowns.
Though arguably it doesn't count, because it's a laptop CPU. They've never done anything similar on desktop, and I don't expect they will any time soon.
To be clear when I said they can't do it, I meant it from a commercial/marketing POV. At normal (for x86) TDP levels they have to compete with AMD's "all our cores are P-cores" and below that is ARM territory. Plus reviewers will eat them alive if they try it on a desktop platform.