Monday, October 21st 2024

Intel "Arrow Lake-H" SKUs Leak: Up to 16 Cores, with LPE Cores Resurfacing

As we await the launch of Intel's "Arrow Lake-S" Core Ultra 200S series of processors for desktops, we are getting some new leaks about Intel's mainstream mobile "Arrow Lake-H" update. A month ago, we got the specification table of the high-end mobile "Arrow Lake-HX," and now, thanks to Jaykihn X, we have the mainstream laptop chip specifications as well. The top-of-the-line includes Intel Core Ultra 9 285H, a 45 W TDP SKU with six P-cores, eight E-cores, and two LPE cores. The CPU packs integrated Xe2 graphics with eight cores and 24 MB of total L3 cache and has a maximum boost of 5.4 GHz for P-cores.

Moving down the stack, there are Core Ultra 7 265H and Core Ultra 5 255H SKUs, which feature the same P/E/LPE core configuration. However, these SKUs are rated for 28 W TDP, having lower maximum frequencies and the same iGPU configuration. This time, we also have two Core Ultra 3 SKUs, with Core Ultra 3 235H and 225H bringing four P-cores, eight E-cores, and two LPE-cores in the 28 W package. The Core Ultra 3 235H has eight Xe2 cores in its iGPU, while the lowest-end Core Ultra 3 225H has only seven Xe2 iGPU cores. For a complete set of specifications, including all clock speeds in base and boost, please check out the table below.
Sources: Jaykihn, via VideoCardz
Add your own comment

8 Comments on Intel "Arrow Lake-H" SKUs Leak: Up to 16 Cores, with LPE Cores Resurfacing

#1
Dirt Chip
What's "LPE"?
I missed this one..
Posted on Reply
#3
tabascosauz
Dirt ChipWhat's "LPE"?
I missed this one..
The new "island" E-cores that came with Meteor Lake and disaggregation. They're not on the compute tile with the rest of the cores, instead they are integrated into the SOC tile (ie. Intel's IO die).

Basically even more E-core than E-cores, to get the most [idle and low load] efficiency out of laptop silicon that have the LP E-cores. More efficiency-oriented V-F curve than the regular E-cores with separate voltage regulation, and obviously its voltage/power is not reliant on what the compute tile is doing at the time.
Posted on Reply
#4
Quicks
Intel losing the plot, they should rather focus on getting their P cores more efficient. All these other E cores not doing Intel any favours with heat and power consumption.
Posted on Reply
#5
Dirt Chip
tabascosauzThe new "island" E-cores that came with Meteor Lake and disaggregation. They're not on the compute tile with the rest of the cores, instead they are integrated into the SOC tile (ie. Intel's IO die).

Basically even more E-core than E-cores, to get the most [idle and low load] efficiency out of laptop silicon that have the LP E-cores. More efficiency-oriented V-F curve than the regular E-cores with separate voltage regulation, and obviously its voltage/power is not reliant on what the compute tile is doing at the time.
So Low Power Ecores, as I suspected
Posted on Reply
#6
Evrsr
This is just Meteor Lake H rebranded. Specs like cores and cache match.
Posted on Reply
#7
londiste
tabascosauzThe new "island" E-cores that came with Meteor Lake and disaggregation. They're not on the compute tile with the rest of the cores, instead they are integrated into the SOC tile (ie. Intel's IO die).

Basically even more E-core than E-cores, to get the most [idle and low load] efficiency out of laptop silicon that have the LP E-cores. More efficiency-oriented V-F curve than the regular E-cores with separate voltage regulation, and obviously its voltage/power is not reliant on what the compute tile is doing at the time.
That is actually a pretty nifty idea. This should allow powering down compute tiles and only leaving SOC tile powered at idle. And SOC tile is the only one that needs to be. No idea whether this actually works all that well in reality though.
Posted on Reply
#8
_roman_
ChaitanyaEven more lower power consumping cores than E core, here is an article from MSI explaining that:
I'll watch and see how the software support is for processors with mixed cores and for processors with many cores.

My software will crash on processors with mixed cores which have mixed instruction sets.
Posted on Reply
Oct 25th, 2024 19:45 EDT change timezone

New Forum Posts

Popular Reviews

Controversial News Posts