Yangtze Memory Technologies Co. has begun shipping its fifth-generation 3D NAND memory chips, featuring 294 total layers and 232 active layers, according to an analysis from TechInsights. The new chips achieve bit density near 20 Gb per square millimeter (19.8 Gb/mm²), comparable to current offerings from SK Hynix and approaching Kioxia/Western Digital's latest products. YMTC's design uses hybrid bonding to connect the memory array with logic components, suggesting that Chinese memory makers are up to speed on the packaging standards that their non-sanctioned competitors use. The company has opted for a quiet release without formal announcements, a departure from typical industry practice. This low-key approach may be related to ongoing US trade restrictions on Chinese semiconductor companies.

While not setting records for active layers, SK Hynix's upcoming 321-layer chip leads in that metric, and YMTC's achievement in total layer count demonstrates continued technical progress. The chip uses string stacking technology, though the specific configuration of the layer arrays remains unclear. Other specifications show the new chip employs YMTC's Xtacking 4.0 architecture and triple-level cell (TLC) design. This matches major competitors' architecture type, though detailed performance metrics such as interface speeds have not been disclosed. The 5th generation NAND focuses on getting density on the right track. However, we expect YMTC to continue development at the same speed, match SK Hynix with 321-layer chips, and surpass it with Xtacking 5.0 in the near future.