Based on multiple reports out of Taiwan, TSMC is seeing increased utilisation of its 3 nm node and its production line is now at close to 50 percent utilisation. The main customer here is without a doubt Apple and TSMC is churning out some 50-55,000 wafers a month on its 3 nm node. TSMC is also getting ready to start production on its N3E node later this year, which will see some customers move to the node.

However, it's not all good news, as TSMC is seeing a decline in utilisation on its 5/4 and 7/6 nm nodes as demand has dropped significantly here, with different news outlets reporting different figures. Some are suggesting the 7/6 nm nodes might have dropped as low as to 50 percent utilisation, others mention 70 percent. The 5/4 nm nodes aren't anywhere nearly as badly affected and remain at around 80 percent utilisation. The good news for TSMC is that this is expected to be a temporary slump in demand and most of its leading edge nodes should be back at somewhere around a 90 percent utilisation rate by the second half of the year. However, this depends on what the demand for its partners' products will look like going forward, as many of TSMC's customers are seeing lower demand for their products in turn.

There are two distinct developments in the client processor space for AMD—first, its Ryzen 7000X3D desktop processors have managed to retain gaming performance competitiveness against Intel's fastest 13th Gen Core "Raptor Lake" processors; and second, that its Ryzen 7045HX "Dragon Range" mobile processors are picking up interest in the enthusiast-segment notebook community, where its advanced 5 nm + 6 nm process is dealing damage to 13th Gen Core mobile processors in performance/Watt, and gaming performance. Can AMD dial things up a notch? Technically, yes.

It should technically be possible for AMD to build "Dragon Range" multi-chip modules using "Zen 4" + 3D Vertical Cache CCDs (CPU complex dies), much in the same way it did for the desktop product stack. Such a processor would either have one CCD with the 3DV cache for a CPU core-count of up to 8-core/16-thread; or a contraption similar to the desktop 7950X3D, wherein one of the CCDs has 3DV cache, while the other is a regular "Zen 4" CCD, for core-counts of up to 16-core/32-thread. But will AMD build such chips? A lot would depend on the volumes of L3Ds (the 6 nm dies with the 64 MB 3D Vertical cache memory that operates at 2.5 TB/s), the production of CCDs with 3DV cache; and whether AMD is able to achieve the right performance/Watt numbers against Intel's fastest 8P+16E "Raptor Lake" mobile processors.

AMD's next-generation RDNA4 graphics architecture will retain a design-focus on gaming performance, without being drawn into an AI feature-set competition with rival NVIDIA. David Wang, SVP Radeon Technologies Group; and Rick Bergman, EVP of Computing and Graphics Business at AMD; gave an interview to Japanese tech publication 4Gamers, in which they dropped the first hints on the direction which the company's next-generation graphics architecture will take.

While acknowledging NVIDIA's movement in the GPU-accelerated AI space, AMD said that it didn't believe that image processing and performance-upscaling is the best use of the AI-compute resources of the GPU, and that the client segment still hasn't found extensive use of GPU-accelerated AI (or for that matter, even CPU-based AI acceleration). AMD's own image processing tech, FSR, doesn't leverage AI acceleration. Wang said that with the company introducing AI acceleration hardware with its RDNA3 architecture, he hopes that AI is leveraged in improving gameplay—such as procedural world generation, NPCs, bot AI, etc; to add the next level of complexity; rather than spending the hardware resources on image-processing.

Intel's upcoming Meteor Lake processor family is supposedly looking good with the new performance/efficiency targets. According to the @OneRaichu Twitter account, we have a potential performance estimate for the upcoming SKUs. As the latest information notes, Intel's 14th-generation Meteor Lake will feature around a 50% increase in efficiency compared to the 13th-generation Raptor Lake designs. This means that the processor can use half the power at the same performance target at Raptor Lake, increasing efficiency. Of course, the design also offers some performance improvements besides efficiency that are significant and are yet to be shown. The new Redwood Cove P-cores will be combined with the new Crestmont E-cores for maximum performance inside U/P/H configurations with 15-45 Watt power envelopes.

For integrated graphics, the source notes that Meteor Lake offers twice the performance of iGPU found on Raptor Lake designs. Supposedly, Meteor Lake will feature 128 EUs running 2.0+GHz compared to 96 EUs found inside Raptor Lake. The iGPU architecture will switch from Intel Iris to Xe-LPG 'Xe-MTL' family on the 14th gen models, confirming a giant leap in performance that iGPU is supposed to experience. Using the tile-based design, Intel combines the Intel 4 process for the CPU tile and the TSMC 5 nm process for the GPU tile. Intel handles final packaging for additional tuning, and you can see the separation below.

MSI Radeon RX 7900 XTX Gaming Trio Classic, the company's first Radeon 7000 series RDNA3 graphics card, is finally listed online. American retailer Newegg put it up for sale at $1,100, a $100 premium over the $1000 AMD baseline price for the RX 7900 XTX. This is a "sold and shipped by Newegg" listing. MSI showed this card off last month, at the 2023 International CES. It pairs a custom-design PCB with a previous-generation Tri Frozr 2.0 cooling solution—the same one it used with its RX 6950 XT Gaming series. The PCB, however, is an MSI in-house design, with a meaty VRM that draws power from three 8-pin PCIe power connectors, and should hence feature a higher power-limit than the reference-design board, which has been known to scoop out a far greater overclocking headroom on other cards with a similar power setup (such as the ASUS TUF Gaming RX 7900 XTX).

The MSI RX 7900 XTX Gaming Trio Classic comes with clock speeds of 2.30 GHz game, and 2.50 GHz boost, which surprisingly are AMD's reference clocks. Perhaps MSI is saving factory-overclocks for the RX 7900 XTX Gaming X Trio Classic, which it will price even higher. Maxing out the 5 nm "Navi 31" GPU, the RX 7900 XTX offers 6,144 stream processors across 96 RDNA3 compute units, with 96 Ray Accelerators, 384 TMUs, 192 ROPs, and a 384-bit wide GDDR6 memory interface, running 24 GB of memory at 20 Gbps (960 GB/s memory bandwidth).

Samsung Electronics today reported financial results for the fourth quarter and the fiscal year 2022. The Company posted KRW 70.46 trillion in consolidated revenue and KRW 4.31 trillion in operating profit in the quarter ended December 31, 2022. For the full year, it reported 302.23 trillion in annual revenue, a record high and KRW 43.38 trillion in operating profit.

The business environment deteriorated significantly in the fourth quarter due to weak demand amid a global economic slowdown. Earnings at the Memory Business decreased sharply as prices fell and customers continued to adjust inventory. The System LSI Business also saw a decline in earnings as sales of key products were weighed down by inventory adjustments in the industry. The Foundry Business posted a new record for quarterly revenue while profit increased year-on-year on the back of advanced node capacity expansion as well as customer base and application area diversification.

TrendForce's recent analysis of the foundry market reveals that demand continues to slide for all types of mature and advanced nodes. The major IC design houses have cut wafer input for 1Q23 and will likely scale back further for 2Q23. Currently, foundries are expected to maintain a lower-than-ideal level of capacity utilization rate in the first two quarters of this year. Some nodes could experience a steeper demand drop in 2Q23 as there are still no signs of a significant rebound in wafer orders. Looking ahead to the second half of this year, orders will likely pick up for some components that underwent an inventory correction at an earlier time. However, the state of the global economy will remain the largest variable that affect demand, and the recovery of individual foundries' capacity utilization rates will not occur as quickly as expected. Taking these factors into account, TrendForce currently forecasts that global foundry revenue will drop by around 4% YoY for 2023. The projected decline for 2023 is more severe when compared with the one that was recorded for 2019.

During its CES 2023 keynote, AMD announced its latest Instinct MI300 APU, a first of its kind in the data center world. Combining the CPU, GPU, and memory elements into a single package eliminates latency imposed by long travel distances of data from CPU to memory and from CPU to GPU throughout the PCIe connector. In addition to solving some latency issues, less power is needed to move the data and provide greater efficiency. The Instinct MI300 features 24 Zen4 cores with simultaneous multi-threading enabled, CDNA3 GPU IP, and 128 GB of HBM3 memory on a single package. The memory bus is 8192-bit wide, providing unified memory access for CPU and GPU cores. CLX 3.0 is also supported, making cache-coherent interconnecting a reality.

The Instinct MI300 APU package is an engineering marvel of its own, with advanced chiplet techniques used. AMD managed to do 3D stacking and has nine 5 nm logic chiplets that are 3D stacked on top of four 6 nm chiplets with HBM surrounding it. All of this makes the transistor count go up to 146 billion, representing the sheer complexity of a such design. For performance figures, AMD provided a comparison to Instinct MI250X GPU. In raw AI performance, the MI300 features an 8x improvement over MI250X, while the performance-per-watt is "reduced" to a 5x increase. While we do not know what benchmark applications were used, there is a probability that some standard benchmarks like MLPerf were used. For availability, AMD targets the end of 2023, when the "El Capitan" exascale supercomputer will arrive using these Instinct MI300 APU accelerators. Pricing is unknown and will be unveiled to enterprise customers first around launch.

AMD today solved the biggest challenge affecting its mobile processor family against Intel—CPU core-counts in the high-end HX-segment, with the introduction of the new Ryzen 7045HX series "Dragon Range" mobile processors. Based on the "Zen 4" microarchitecture, these processors offer core-counts of up to 16-core/32-thread, and target enthusiast gaming notebooks and mobile workstations. The processors debut the new "Dragon Range" multi-chip module (MCM). This is essentially a non-socketed version of the desktop "Raphael" MCM built in a mobile-friendly BGA package with a thin substrate and no IHS, with up to two 5 nm "Zen 4" 8-core CCDs, and a 6 nm cIOD (client I/O die).

The "Dragon Range" MCM uses the same chiplets as desktop "Raphael" Ryzen 7000 processors, and so its I/O is similar. The cIOD puts out a dual-channel (4 sub-channel) DDR5 memory interface, and a PCI-Express 5.0 x16 interface for discrete graphics, along with two PCI-Express 5.0 x4 links for up to two Gen 5 NVMe SSDs. The platform core-logic (chipset) is functionally similar to the desktop AMD B650E. All processor models in the series come with a TDP of 45 W, and a package power tracking (PPT) of "at least" 75 W. Each "Zen 4" CPU core comes with 1 MB of dedicated L2 cache, and each CCD has 32 MB of L3 cache.

On the day of TSMC's celebration of the mass production start of its 3 nm node, news out of Taiwan suggests that all of its top 10 customers have cut their orders for 2023. However, the cuts are unlikely to affect its new node, but rather its existing nodes, with the 7 and 6 nm nodes said to be hit the hardest, by as much as a 50 percent utilisation reduction in the first quarter of 2023. The 28 nm and 5 and 4 nm nodes are also said to be affected, although it's unclear by how much at this point in time.

Revenue is expected to fall by at least 15 percent in the first quarter of 2023 for TSMC, based on numbers from DigiTimes. The fact that TSMC has increased its 2023 pricing by six percent should at least help offset some of the potential losses for the company, but it all depends on the demand for the rest of the year. Demand for mobile devices is down globally, which is part of the reason why so many of TSMC's customers have cut back their orders, as Apple, Qualcomm and Mediatek all produce their mobile SoCs at TSMC. Add to this that the demand for computers and new computer components are also down, largely due to the current pricing and TSMC is in for a tough time next year.

TSMC today held a 3 nanometer (3 nm) Volume Production and Capacity Expansion Ceremony at its Fab 18 new construction site in the Southern Taiwan Science Park (STSP), bringing together suppliers, construction partners, central and local government, the Taiwan Semiconductor Industry Association, and members of academia to witness an important milestone in the Company's advanced manufacturing.

TSMC has laid a strong foundation for 3 nm technology and capacity expansion, with Fab 18 located in the STSP serving as the Company's GIGAFAB facility producing 5 nm and 3 nm process technology. Today, TSMC announced that 3 nm technology has successfully entered volume production with good yields, and held a topping ceremony for its Fab 18 Phase 8 facility. TSMC estimates that 3 nm technology will create end products with a market value of US$1.5 trillion within five years of volume production.

According to news out of Taiwan, TSMC will hold a ceremony to mark the official mass production start of its 3 nm node on the 29th of December. This is said to help "shatter doubts about de-Taiwanization" or in simpler terms, that Taiwan will lose its golden goose as TSMC invests abroad. The 3 nm fab—known as fab 18—is based in southern Taiwan's Tainan and the ceremony also marks the start of an expansion of TSMC's most advanced fab. TSMC is said to be kicking off its N3E node production sometime in the second half of 2023, followed by its N3P node in 2024, all of which should take place at fab 18, which also produces 5 nm wafers.

In related news, according to Reuters, a Japanese lawmaker from the ruling party has said that TSMC is considering a second plant in Japan, in addition to its current joint venture that is already under construction. TSMC's response to Reuters was that the company isn't ruling out Japan for future fabs, but that the company doesn't have any current plans. At the same time, TSMC is said to be sending executives to Dresden, Germany in early 2023, for a second round of talks about building a fab to help support the European auto industry, although this would be a 28/22 nm fab, which is far from cutting edge these days, although a lot more advanced than most fabs making chips for the auto industry.

Huawei, the Chinese technology giant, has reportedly filed patents that it is developing extreme ultraviolet (EUV) scanners for use in the manufacturing process of semiconductors. This news comes amid increasing tensions between Huawei and the US government, which has imposed a series of sanctions on the company in recent years. According to UDN, Huawei has filed a patent that covers the entire EUV scanner with a 13.5 nm EUV light source, mirrors, lithography for printing circuits, and proper system control. While filing a patent is not the same as creating an accurate EUV scanner, it could enable China to produce a class of chips below 7 nm and have a homegrown semiconductor production, despite the ever-increasing US sanctions.

The development of EUV scanners is a significant milestone for Huawei and the semiconductor industry. However, the company's progress in this area may be hindered by the US government's sanctions, which have limited Huawei's access to certain technologies and markets. It is important to note that Chinese SMIC wanted to develop EUV fabrication based on third-party EUV tools; however, those plans were scrapped as the Wassenaar agreement came into action and prohibited the sales of advanced tools to Chinese companies. Huawei's development could represent a new milestone for the entire Chinese industry.

According to TrendForce's research, the total revenue of the global top 10 foundries rose by 6% QoQ to US$35.21 billion for 3Q22 as the release of the new iPhone series during the second half of the year generated significant stock-up activities across Apple's supply chain. However, the global economy shows weak performances, and factors such as China's policy on containing COVID-19 outbreaks and high inflation continue to impact consumer confidence. As a result, peak-season demand in the second half of the year has been underwhelming, and inventory consumption is proceeding slower than anticipated. This situation has led to substantial downward corrections to foundry orders as well. For 4Q22, TrendForce forecasts that the total revenue of the global top 10 foundries will register a QoQ decline, thereby terminating the boom of the past two years—when there was an uninterrupted trend of QoQ revenue growth.

Regarding individual foundries' performances in 3Q22, the group of the top five was led by TSMC, followed by Samsung, UMC, GlobalFoundries, and SMIC. Their collective global market share (in revenue terms) came to 89.6%. Most foundries were directly impacted by clients slowing down their stock-up activities or significantly correcting down their orders. Only TSMC was able to make a notable gain due to Apple's strong stock-up demand for the SoCs deployed in this year's new iPhone models. TSMC saw its revenue rise by 11.1% QoQ to US$20.16 billion, and the corresponding market share expanded to 56.1%. The growth was mainly attributed to the ≤7 nm nodes, whose share in the foundry's revenue had kept climbing and reached 54% in the third quarter. Conversely, Samsung actually experienced a slight QoQ drop of 0.1% in foundry revenue even though it had also benefited from the component demand related to the new iPhone series. Partially impacted by the weakening of the Korean won, Samsung's market share fell to 15.5%.

Apple and NVIDIA will be among the first customers of TSMC's swanky new $12 billion semiconductor fab in Arizona, USA. Apple will be the first major player to kick off mass-production in the fab, and will be closely followed by NVIDIA. Both companies plan to produce some of their inventory in Arizona, and ramp proportionately up as the fab grows in capacity.

The plan with TSMC's Arizona fab was to originally make 5 nm and 4 nm EUV chips, with an output of 20,000 wafers a month, but the company now expects to deploy a more advanced node to keep up with what will be considered cutting-edge when the fab goes live (think 2 nm-class); and also double the output to 40,000 wafers a month. The capacity should ensure Apple and NVIDIA make their most cutting-edge chips on the node (away from Asia), so there could be tighter export controls, and build supply-chain resilience in the face of security problems arising in the Taiwan straits.

The unified shader (stream processor) counts of AMD's upcoming second- and third-largest GPUs based on the RDNA3 graphics architecture, have been leaked in some ROCm code, discovered by Kepler_L2 on Twitter. The "performance.hpp" file references "Navi 32" with a compute unit count of 60, and the "Navi 33" with 32 compute units. We know from the "Navi 31" specifications that an RDNA3 compute unit still amounts to 64 stream processors (although with significant IPC uplifts over the RDNA2 stream processor due to dual-instruction issue-rate).

60 compute units would give the "Navi 32" silicon a stream processor count of 3,840, a 50% numerical increase over the 2,560 of its predecessor, the "Navi 22," powering graphics cards such as the Radeon RX 6750 XT. Meanwhile, the 32 CU count of the "Navi 33" amounts to 2,048 stream processors, which is numerically unchanged from that of the "Navi 23" powering the RX 6650 XT. The new RDNA3 compute unit has significant changes over RDNA2, besides the dual-issue stream processors—it gets second-generation Ray Accelerators, and two AI accelerators for matrix-multiplication.

Semiconductor manufacturing is a significant investment that requires long lead times and constant improvement. According to the latest DigiTimes report, the pricing of a 3 nm wafer is expected to reach $20,000, which is a 25% increase in price over a 5 nm wafer. For 7 nm, TSMC managed to produce it for "just" $10,000; for 5 nm, it costs the company to make it for the $16,000 mark. And finally, the latest and greatest technology will get an even higher price point at $20,000, a new record in wafer pricing. Since TSMC has a proven track record of delivering constant innovation, clients are expected to remain on the latest tech purchasing spree.

Companies like Apple, AMD, and NVIDIA are known for securing orders for the latest semiconductor manufacturing node capacities. With a 25% increase in wafer pricing, we can expect the next-generation hardware to be even more expensive. Chip manufacturing price is a significant price-determining factor for many products, so the 3 nm edition of CPUs, GPUs, etc., will get the highest difference.

Although Morris Chang is no longer in charge of the day to day business at TSMC, the founder of the company is still getting his hands dirty. Chang attended the APEC Economic Leaders Meeting last week, as part of Taiwan's delegation and was questioned by the media about TSMC's future plans. The specific question was about TSMC's Arizona fab, which will initially produce chips using a 5 nm node. The US$12 billion plant is scheduled to kick off production at some point in 2024, by which time the 5 nm node should be a commonly used node rather than close to cutting edge.

When questioned about the future of the Arizona fab, Morris Chang answered that it will be moving to a 3 nm node, which is currently TSMC's most cutting edge node, that has gone into volume production earlier this year with th N3 node, which is set to be followed by the N3E node. According to Chang, there's interest by several countries to have TSMC set up fabs there, but apparently this is not something TSMC is considering at the moment. One potential reason for this would be a suitable labour force, something that has already proven to be tough for the Arizona fab.

AMD, in its technical presentation for the new Radeon RX 7900 series "Navi 31" GPU, gave us an elaborate explanation on why it had to take the chiplets route for high-end GPUs, devices that are far more complex than CPUs. The company also enlightened us on what sets chiplet-based packages apart from classic multi-chip modules (MCMs). An MCM is a package that consists of multiple independent devices sharing a fiberglass substrate.

An example of an MCM would be a mobile Intel Core processor, in which the CPU die and the PCH die share a substrate. Here, the CPU and the PCH are independent pieces of silicon that can otherwise exist on their own packages (as they do on the desktop platform), but have been paired together on a single substrate to minimize PCB footprint, which is precious on a mobile platform. A chiplet-based device is one where a substrate is made up of multiple dies that cannot otherwise independently exist on their own packages without an impact on inter-die bandwidth or latency. They are essentially what should have been components on a monolithic die, but disintegrated into separate dies built on different semiconductor foundry nodes, with a purely cost-driven motive.

Eliyan Corporation, credited for the invention of the semiconductor industry's highest-performance and most efficient chiplet interconnect, today announced two major milestones in the commercialization of its technology for multi-die chiplet integration: the close of its Series A $40M funding round, and the successful tapeout of its technology on an industry standard 5-nanometer (nm) process.

Eliyan's NuLink PHY and NuGear technologies address the critical need for a commercially viable approach to enabling high performance and cost-effectiveness in the connection of homogeneous and heterogenous architectures on a standard, organic chip substrate. It has proven to achieve similar bandwidth, power efficiency, and latency as die-to-die implementations using advanced packaging technologies, but without the other drawbacks of specialized approaches.

An alleged leaked company slide details AMD's upcoming 5 nm "Navi 31" GPU powering the next-generation Radeon RX 7900 XTX and RX 7900 XT graphics cards. The slide details the "Navi 31" MCM, with its central graphics compute die (GCD) chiplet that's built on the 5 nm EUV silicon fabrication process, surrounded by six memory cache dies (MCDs), each built on the 6 nm process. The GCD interfaces with the system over a PCI-Express 4.0 x16 host interface. It features the latest-generation multimedia engine with dual-stream encoders; and the new Radiance display engine with DisplayPort 2.1 and HDMI 2.1a support. Custom interconnects tie it with the six MCDs.

Each MCD has 16 MB of Infinity Cache (L3 cache); and a 64-bit GDDR6 memory interface (two 32-bit GDDR6 paths). Six of these add up to the GPU's 384-bit GDDR6 memory interface. In the scheme of things, the GPU has a contiguous and monolithic 384-bit wide memory bus, because every modern GPU uses multiple on-die memory controllers to achieve a wide memory bus. "Navi 31" hence has a total Infinity Cache size of 96 MB—which may be less in comparison to the 128 MB on "Navi 21," but AMD has shored up cache sizes across the GPU. The L0 caches on the compute units is now increased numerically by 240%. The L1 caches by 300%, and the L2 cache shared among the shader engines, by 50%. The RX 7900 XTX is confirmed to use 20 Gbps GDDR6 memory in this slide, for 960 GB/s of memory bandwidth.

AMD today announced the Radeon RX 7900 XTX and Radeon RX 7900 XT gaming graphics cards debuting its next-generation RDNA3 graphics architecture. The two new cards come at $999 and $899—basically targeting the $1000 high-end premium price point.Both cards will be available on December 13th, not only the AMD reference design, which is sold through AMD.com, but also custom-design variants from the many board partners on the same day. AIBs are expected to announce their products in the coming weeks.The RX 7900 XTX is priced at USD $999, and the RX 7900 XT is $899, which is a surprisingly small difference of only $100, for a performance difference that will certainly be larger, probably in the 20% range. Both Radeon RX 7900 XTX and RX 7900 XT are using the PCI-Express 4.0 interface, Gen 5 is not supported with this generation. The RX 7900 XTX has a typical board power of 355 W, or about 95 W less than that of the GeForce RTX 4090. The reference-design RX 7900 XTX uses conventional 8-pin PCIe power connectors, as would custom-design cards, when they come out. AMD's board partners will create units with three 8-pin power connectors, for higher out of the box performance and better OC potential. The decision to not use the 16-pin power connector that NVIDIA uses was made "well over a year ago", mostly because of cost, complexity and the fact that these Radeons don't require that much power anyway.

Here's the first picture of the "Navi 31" GPU at the heart of AMD's fastest next-generation graphics cards. Based on the RDNA3 graphics architecture, this will mark an ambitious attempt by AMD to build the first multi-chip module (MCM) client GPU featuring more than one logic die. MCM GPUs aren't new in the enterprise space with Intel's "Ponte Vecchio," but this would be the first such GPU meant for hardcore gaming graphics products. AMD had made MCM GPUs in the past, but those have been packages with just one logic die, surrounded by memory stacks. "Navi 31" is an MCM of as many as eight logic dies, and no memory stacks (no, those aren't HBM stacks in the picture below).

It's rumored that "Navi 31" features one or two SIMD chiplets dubbed GCDs, featuring the GPU's main number crunching machinery, the RDNA3 compute units. These chiplets are likely built on the most advanced silicon fabrication node, likely TSMC 5 nm EUV, but we'll see. The GDDR6 memory controllers handling the chip's 384-bit wide GDDR6 memory interface, will be located on separate chiplets built on a slightly older node, such as TSMC 6 nm. This is not multi-GPU-a-stick, because both SIMD chiplets have uniform access to the entire 384-bit wide memory bus (which is not 2x 192-bit but 1x 384-bit), besides the other ancillaries. The "Navi 31" MCM are expected to be surrounded by JEDEC-standard 20 Gbps GDDR6 memory chips.

AMD (NASDAQ:AMD) today announced revenue for the third quarter of 2022 of $5.6 billion, gross margin of 42%, operating loss of $64 million, net income of $66 million and diluted earnings per share of $0.04. On a non-GAAP(*) basis, gross margin was 50%, operating income was $1.3 billion, net income was $1.1 billion and diluted earnings per share was $0.67.

"Third quarter results came in below our expectations due to the softening PC market and substantial inventory reduction actions across the PC supply chain," said AMD Chair and CEO Dr. Lisa Su. "Despite the challenging macro environment, we grew revenue 29% year-over-year driven by increased sales of our data center, embedded and game console products. We are confident that our leadership product portfolio, strong balance sheet, and ongoing growth opportunities in our data center and embedded businesses position us well to navigate the current market dynamics."

SiFive, Inc. the founder and leader of RISC-V computing, today announced two new products that address the need for high performance and efficiency in a small size in high volume applications like wearables, smart home, industrial automation, AR/VR, and other consumer devices. The SiFive Performance P670 and P470 RISC-V processors bring unparalleled compute performance and efficiency that is significantly raising the bar for innovative designs in these high-volume markets. The modern and innovative SiFive design methodologies bring raw compute density that is a substantial advantage for SiFive Performance products and also translates into significant cost savings for customers.

"The P670 and P470 are specifically designed for, and capable of handling the most demanding workloads for wearables and other advanced consumer applications. These new products offer powerful performance and compute density for companies looking to upgrade from legacy ISAs," said Chris Jones, SiFive VP of Product. "We have optimized these new RISC-V Vector enabled products to deliver the performance and efficiency improvements the industry has long been asking for, and we are in evaluations with a number of top-tier customers. Additionally, as the upstream enablement of RISC-V has started within the Android Open Source Project, (AOSP), designers will have unrivaled choice and flexibility as they consider the positive implications with that platform for future designs."