Earlier this week, we brought you a report about codenames of AMD processors that won't launch before 2022. It referenced "Raphael" being distant 5 nm "Zen 4" based successor to today's "Matisse." At the time, the codename for the 2021 release of AMD's mainstream desktop processor wasn't known. We're now getting a pointer as to what it is - "Warhol."

Named after American artist and filmmaker Andy Warhol, this processor combines CPU chiplets based on the "Zen 3" with a cIOD that retains PCI-Express gen 4.0, just like "Vermeer," but still qualifies as a new generation (and not a refresh). What's more, "Warhol" apparently sticks to a 7 nm-class silicon fabrication process. This means that "Warhol" could see AMD innovate on other fronts, such as leveraging an even more advanced version of TSMC's 7 nm node (such as N7+), to increase core counts over the chiplet that makes it to "Vermeer, "Genesis Peak," and "Milan."

Several future AMD processor codenames across various computing segments surfaced courtesy of an Expreview leak that's largely aligned with information from Komachi Ensaka. It does not account for "Matisse Refresh" that's allegedly coming out in June-July as three gaming-focused Ryzen socket AM4 desktop processors; but roadmap from 2H-2020 going up to 2022 sees many codenames surface. To begin with, the second half of 2020 promises to be as action packed as last year's 7/7 mega launch. Over in the graphics business, the company is expected to debut its DirectX 12 Ultimate-compliant RDNA2 client graphics, and its first CDNA architecture-based compute accelerators. Much of the processor launch cycle is based around the new "Zen 3" microarchitecture.

The server platform debuting in the second half of 2020 is codenamed "Genesis SP3." This will be the final processor architecture for the SP3-class enterprise sockets, as it has DDR4 and PCI-Express gen 4.0 I/O. The EPYC server processor is codenamed "Milan," and combines "Zen 3" chiplets along with an sIOD. EPYC Embedded (FP6 package) processors are codenamed "Grey Hawk."

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today announced plans to boost its foundry capacity at the company's new production line in Pyeongtaek, Korea, to meet growing global demand for cutting-edge extreme ultraviolet (EUV) solutions.

The new foundry line, which will focus on EUV-based 5 nanometer (nm) and below process technology, has just commenced construction this month and is expected to be in full operation in the second half of 2021. It will play a pivotal role as Samsung aims to expand the use of state-of-the-art process technologies across a myriad of current and next generation applications, including 5G, high-performance computing (HPC) and artificial intelligence (AI).

It has become a matter of national strategy (or pride) to get TSMC to build a cutting-edge silicon fabrication facility on U.S. soil. Hot on the heals of a report in which TSMC denied it has any plans to build a fab in the U.S., we're learning from a Wall Street Journal that the world's largest independent semiconductor manufacturing company, will build a facility in the U.S. after all. Apparently TSMC will build a silicon fabrication facility in the state of Arizona. The fab will manufacture 5 nm-class chips, to begin with.

TSMC got around to drawing up plans to build a stateside facility after the "involvement" of the State- and Commerce Departments of the U.S. Government. The two are involved not just in coaxing TSMC, but also in the specifics of the planning to get them to the Grand Canyon state. The Donald Trump administration made significant national policy changes with manufacturing, in the wake of the COVID-19 pandemic causing significant wait times in getting silicon products from Asia to the US.Update 01:25 UTC: TSMC made its U.S. fab plans official with an announcement. Press release and additional commentary below.

A DigiTimes premium report, interpreted by Chiakokhua, aka Retired Engineer, chronicling NVIDIA's move to contract TSMC for 7 nm and 5 nm EUV nodes for GPU manufacturing, made a startling revelation about NVIDIA's recent foundry diversification moves. Back in July 2019, a leading Korean publication confirmed NVIDIA's decision to contract Samsung for its next-generation GPU manufacturing. This was a week before AMD announced its first new-generation 7 nm products built for the TSMC N7 node, "Navi" and "Zen 2." The DigiTimes report reveals that NVIDIA underestimated the efficiency gains AMD would yield from TSMC N7.

With NVIDIA's bonhomie with Samsung underway, and Apple transitioning to TSMC N5, AMD moved in to quickly grab 7 nm-class foundry allocation and gained prominence with the Taiwanese foundry. The report also calls out a possible strategic error on NVIDIA's part. Upon realizing the efficiency gains AMD managed, NVIDIA decided to bet on TSMC again (apparently without withdrawing from its partnership with Samsung), only to find that AMD had secured a big chunk of its nodal allocation needed to support its growth in the x86 processor and discrete GPU markets. NVIDIA has hence decided to leapfrog AMD by adapting its next-generation graphics architectures to TSMC's EUV nodes, namely the N7+ and N5. The report also speaks of NVIDIA using its Samsung foundry allocation as a bargaining chip in price negotiations with TSMC, but with limited success as TSMC established its 7 nm-class industry leadership. As it stands now, NVIDIA may manufacture its 7 nm-class and 5 nm-class GPUs on both TSMC and Samsung.

Samsung in its Q1-2020 financials release disclosed that the company will commence mass production of chips on its cutting-edge 5 nanometer EUV silicon fabrication process within Q2-2020 (that's before July 2020). This is big, as it lends credence to rumors of NVIDIA secretly developing 5 nm GPUs. Suddenly, it's possible that "Ampere," if not "Hopper," is 5 nm EUV-based, as NVIDIA has chosen Samsung to be its foundry partner for next-generation GPUs.

"In the second quarter, the Company aims to expand EUV leadership, beginning with the start of mass production of 5 nm products, while closely monitoring the uncertain market situation caused by COVID-19," the company states in the release. Samsung also announced that following commencement of mass production on 5 nm, further development of GAAFET (gate all-around FET) 3 nanometer silicon fabrication process will get underway. The company appears to be erring on the side of caution with its forward-looking statements, though. Much of what Samsung does will be dictated by the impact of COVID-19 on the supply chain and market.

AMD is expected to support the next-generation DDR5 memory standard by 2022, according to a MyDrivers report citing industry sources. We are close to a change in memory standards, with the 5-year old DDR4 memory standard beginning a gradual phase out over the next 3 years. Leading DRAM manufacturers such as SK Hynix have already hinted mass-production of the next-generation DDR5 memory to commence within 2020. Much like with DDR4, Intel could be the first to market with processors that support it, likely with its "Sapphire Rapids" Xeon processors. AMD, on the other hand, could debut support for the standard only with its "Zen 4" microarchitecture slated for 2021 technology announcements, with 2022 availability.

AMD "Zen 4" will see a transition to a new silicon fabrication process, likely TSMC 5 nm-class. It will be an inflection point for the company from an I/O standpoint, as it sees the introduction of DDR5 memory support across enterprise and desktop platforms, LPDDR5 on the mobile platform, and PCI-Express gen 5.0 across the board. Besides a generational bandwidth doubling, PCIe gen 5.0 is expected to introduce several industry-standard features that help with hyper-scalability in the enterprise segment, benefiting compute clusters with multiple scalar processors, such as AMD's CDNA2. Intel introduced many of these features with its proprietary CXL interconnect. AMD's upcoming "Zen 3" microarchitecture, scheduled for within 2020 with market presence in 2021, is expected to stick with DDR4, LPDDR4x, and PCI-Express gen 4.0 standards. DDR5 will enable data-rates ranging between 3200 to 8400 MHz, densities such as single-rank 32 GB UDIMMs, and a few new physical-layer features such as same-bank refresh.

A report via DigiTimes places TSMC as having announced to its investors that exploratory studies and R&D for the development of the 2 nm process node have commenced. As today's leading semiconductor fabrication company, TSMC doesn't seem to be one resting on its laurels. Their 7 nm process and derivatives have already achieved a 30% weight on the company's semiconductor orders, and their 5 nm node (which will include EUV litography) is set to hit HVM (High Volume Manufacturing) in Q2 of this year. Apart from that, not much more is known on 2 nm.

After 5 nm, which is expected to boats of an 84-87% transistor density gain over the current 7nm node, the plans are to go 3nm, with TSMC expecting that node to hit mass production come 2022. Interestingly, TSMC is planning to still use FinFET technology for its 3 nm manufacturing node, though in a new GAAFET (gate-all-around field-effect transistor) technology. TSMC's plans to deploy FinFET in under 5nm manufacturing is something that many industry analysts and specialist thought extremely difficult to achieve, with expectations for these sub-5nm nodes to require more exotic materials and transistor designs than TSMC's apparent plans

According to the report of DigiTimes, which talked about TSMC's 5 nm silicon manufacturing node, they have reported that NVIDIA is also going to be a customer for it and they could use it in the near future. And that is very interesting information, knowing that these chips will not go in the next generation of GPUs. Why is that? Because we know that NVIDIA will utilize both TSMC and Samsung for their 7 nm manufacturing nodes for its next-generation Ampere GPUs that will end up in designs like GeForce RTX 3070 and RTX 3080 graphics cards. These designs are not what NVIDIA needs 5 nm for.

Being that NVIDIA already has a product in its pipeline that will satisfy the demand for the high-performance graphics market, maybe they are planning something that will end up being a surprise to everyone. No one knows what it is, however, the speculation (which you should take with a huge grain of salt) would be that NVIDIA is updating its Tegra SoC with the latest node. That Tegra SoC could be used in a range of mobile devices, like the Nintendo Switch, so could NVIDIA be preparing a new chip for Nintendo Switch 2?

Imagine being able to shrink a Pentium 4 processor die to the size of a pin-head (if you can figure out how to place 478 bumps on it). TSMC revealed that its future 3 nanometer silicon fabrication node has a development target of 250 million transistors per mm². Called N3, the next-generation silicon fabrication node succeeds TSMC's N5 family of 5 nm-class nodes (that's N5 and any possible refinements).

TSMC CEO CC Wei confirmed that development of the 3 nm node is on-track, with risk production scheduled for 2021 and volume production commencing in the second half of 2022. Perhaps the most startling revelation is that TSMC has decided to stick with FinFETs for N3 owing to the maturity of the technology. Experts are of the opinion that sub-5 nm nodes will require major innovations with materials and structures. TSMC claims that N3 will provide a 10-15% speed improvement at iso-power or 25-30% power reduction at iso-speed, compared to N5.

With Mainland Chinese tech giant Huawei being effectively cut off from contracting Taiwanese TSMC to manufacture its next-generation HiSilicon 5G mobile SoCs, and NVIDIA switching to Samsung for its next-generation GPUs, TSMC is looking to hold on to large high-volume customers besides Apple and Qualcomm, so as to not let them dictate pricing. AMD is at the receiving end of the newfound affection, with the semiconductor firm reportedly developing a new refinement of its 5 nm node specially for AMD, possibly to make Sunnyvale lock in on TSMC for its future chip architectures. A ChainNews report decoded by @chiakokhua sheds light on this development.

AMD is developing its "Zen 4" CPU microarchitecture for a 5 nm-class silicon fabrication node, although the company doesn't appear to have zeroed in on a node for its RDNA3 graphics architecture and CDNA2 scalar compute architecture. In its recent public reveal of the two, AMD chose not to specify the foundry node for the two, which come out roughly around the same time as "Zen 4." It wouldn't be far fetched to predict that AMD and TSMC were waiting on certainty for the new 5 nm-class node's development. There are no technical details of this new node. AMD's demand for TSMC is expected to be at least 20,000 12-inch wafers per month.

TSMC will be doing good on their previous expectations for a H2 2020 ramp-up for high volume production (HVM) on their 5 nm manufacturing process. The new 5 nm fabrication process is an Extreme Ultraviolet lithography (EUV) one, with up to 14 layers being etchable onto the silicon wafers, as opposed to five and six, respectively, for TSMC's N7+ and N6 processes.

Volume production will start with Apple's A14 SoC, meant to be driving next-generation iPhones that should hit shelves by September this year (should the COVID-19 pandemic let it be so). Apple is using two thirds of TSMC's capacity for 5 nm as is with this SoC; it's currently unclear which client (or clients) are getting the leftover one third capacity. TSMC announced back in December that they were seeing yields upwards of 80% in 5 nm EUV fabrication, so now it's "just" a matter of monetizing the process until their 3 nm iteration comes online, expectedly, in 2022.

With its 7 nm RDNA architecture that debuted in July 2019, AMD achieved a nearly 50% gain in performance/Watt over the previous "Vega" architecture. At its 2020 Financial Analyst Day event, AMD made a big disclosure: that its upcoming RDNA2 architecture will offer a similar 50% performance/Watt jump over RDNA. The new RDNA2 graphics architecture is expected to leverage 7 nm+ (7 nm EUV), which offers up to 18% transistor-density increase over 7 nm DUV, among other process-level improvements. AMD could tap into this to increase price-performance by serving up more compute units at existing price-points, running at higher clock speeds.

AMD has two key design goals with RDNA2 that helps it close the feature-set gap with NVIDIA: real-time ray-tracing, and variable-rate shading, both of which have been standardized by Microsoft under DirectX 12 DXR and VRS APIs. AMD announced that RDNA2 will feature dedicated ray-tracing hardware on die. On the software side, the hardware will leverage industry-standard DXR 1.1 API. The company is supplying RDNA2 to next-generation game console manufacturers such as Sony and Microsoft, so it's highly likely that AMD's approach to standardized ray-tracing will have more takers than NVIDIA's RTX ecosystem that tops up DXR feature-sets with its own RTX feature-set.

AMD at its 2020 Financial Analyst Day event unveiled its upcoming CDNA GPU-based compute accelerator architecture. CDNA will complement the company's graphics-oriented RDNA architecture. While RDNA powers the company's Radeon Pro and Radeon RX client- and enterprise graphics products, CDNA will power compute accelerators such as Radeon Instinct, etc. AMD is having to fork its graphics IP to RDNA and CDNA due to what it described as market-based product differentiation.

Data centers and HPCs using Radeon Instinct accelerators have no use for the GPU's actual graphics rendering capabilities. And so, at a silicon level, AMD is removing the raster graphics hardware, the display and multimedia engines, and other associated components that otherwise take up significant amounts of die area. In their place, AMD is adding fixed-function tensor compute hardware, similar to the tensor cores on certain NVIDIA GPUs.

TSMC today announced it has collaborated with Broadcom on enhancing the Chip-on-Wafer-on-Substrate (CoWoS ) platform to support the industry's first and largest 2X reticle size interposer. With an area of approximately 1,700mm2, this next generation CoWoS interposer technology significantly boosts computing power for advanced HPC systems by supporting more SoCs as well as being ready to support TSMC's next-generation five-nanometer (N5) process technology.

This new generation CoWoS technology can accommodate multiple logic system-on-chip (SoC) dies, and up to 6 cubes of high-bandwidth memory (HBM), offering as much as 96 GB of memory. It also provides bandwidth of up to 2.7 terabytes per second, 2.7 times faster than TSMC's previously offered CoWoS solution in 2016. With higher memory capacity and bandwidth, this CoWoS solution is well-suited for memory-intensive workloads such as deep learning, as well as workloads for 5G networking, power-efficient datacenters, and more. In addition to offering additional area to increase compute, I/O, and HBM integration, this enhanced CoWoS technology provides greater design flexibility and yield for complex ASIC designs in advanced process nodes.

Apple is currently designing a custom series of CPUs, for its Macbook laptop lineup, based on the Arm Instruction Set Architecture. Having designed some of the most powerful mobile processors that are inside the iPhone series of devices, Apple is preparing to make a jump to an even more powerful device lineup by bringing custom CPUs for MacBook. Tired of the speed by which Intel replaces and upgrades its Core lineup of CPUs, Apple decided to take the matter in its own hands and rumors about the switch to a custom solution have been going on for a while. However, we now have some information about when to expect the first wave of Arm-powered Macs.

According to the analyst Ming-Chi Kuo, who is a well-known insider in the Apple industry, we can expect the first wave of the Arm-powered Macbook in the next 18 months, precisely in the first half of 2021. Supposedly, the first chips for these new Macs are going to be manufactured on a 5 nm manufacturing process, possibly over at TSMC since Apple had a long-lasting history of manufacturing its chips at TSMC foundries. In the meantime, we can expect to see Apple providing developers with tools to transition their x86-64 software to the new Arm ISA. Without a software ecosystem, the hardware platform is essentially worthless. And Apple knows this. We will see how they plan to play it and will report as soon as there is more information.

AMD in the second half of 2020 could outpace Apple as the biggest foundry customer of TSMC for its 7 nm silicon fabrication nodes (DUV and EUV combined). There are two key factors contributing to this: AMD significantly increasing its orders for the year; and Apple transitioning to TSMC's 5 nm node for its A14 SoC, freeing up some 7 nm allocation, which AMD grabbed. AMD is currently tapping into 7 nm DUV for its "Zen 2" chiplet, "Navi 10," and "Navi 14" GPU dies. The company could continue to order 7 nm DUV until these products reach EOL; while also introducing the new "Renoir" APU die on the process. The foundry's new 7 nm+ (EUV) node will be utilized for "Zen 3" chiplets and "Navi 2#" GPU dies in 2020.

Currently, the top-5 customers for TSMC 7 nm are Apple, HiSilicon, Qualcomm, AMD, and MediaTek. Barring AMD, the others in the top-5 build mobile SoCs or 4G/5G modem chips on the node. AMD is expected to top the list as it scales up orders with TSMC. In the first half of 2020, TSMC's monthly output for 7 nm is expected to grow to 110,000 wafers per month (wpm). Apple's migration to 5 nm in 2H-2020, coupled with capacity-addition could take TSMC's 7 nm output to 140,000 wpm. AMD has reportedly booked the entire capacity-addition for 30,000 wpm, taking its allocation up to 21% in 2H-2020. Qualcomm is switching to Samsung for its next-generation SoCs and modems designed for 7 nm EUV. NVIDIA, too, is expected to built its next-gen 7 nm EUV GPUs on Samsung instead of TSMC. These moves by big players could free up significant foundry allocation at TSMC for AMD's volumes to grow in 2020.

AMD's "Zen 4" CPU microarchitecture is on track for a 2021 launch as its principal foundry partner, TSMC, is optimistic about early yields of its 5 nm silicon fabrication node. TSMC supports the 5 nm product roadmaps of not just AMD, but also Apple and HiSilicon. "Zen 4" is particularly important for AMD, as it will release its next enterprise platform, codenamed "Genoa," along with the new SP5 socket. The new socket will present AMD with the opportunity to significantly change the processor's I/O, such as support for a new memory standard, a new PCIe generation, more memory channels, more PCIe lanes, etc. As early as 2019, the foundry is seeing yields of over 50 percent for the 5 nm node (possibly risk production designed to test the node), which is very encouraging for its customers.

AMD's roadmap for 2020 sees the introduction of "Zen 3" on the 7 nm EUV process (dubbed 7 nm+). AMD recently commented that the performance uplift of "Zen 3" versus "Zen 2" will be "right in line with what you would expect from an entirely new architecture." The 7 nm EUV node provides a significant 20 percent increase in transistor-density compared to the current 7 nm DUV node "Zen 2" chiplets and the company's "Navi" family of GPUs are built on. "Zen 3" could see the company do away with the CCX (quad-core CPU complex), and make chiplets monolithic blocks of CPU cores without sub-divisions. For the client-segment, 5 is a recurring number in 2021. It will see the introduction of the 5th generation Ryzen processors (5000-series), built on the 5 nm process, supporting DDR5 memory, PCI-Express gen 5, and the new AM5 client-segment CPU socket.

TSMC is delivering record results day after day, with a 5 nm manufacturing process starting High Volume Manufacturing (HVM) in Q2 next year, 7 nm process getting plenty of orders and the fact that TSMC just became the biggest company publicly trading in Asia. Continuing with the goal to match or even beat the famous Moore's Law, TSMC is already planning for future 3 nm node manufacturing, promised to start HVM as soon as 2022 arrives, according to JK Wang, TSMC's senior vice president of fab operations. Delivering 3 nm a whole year before originally planned in 2023, TSMC is working hard, with fab construction work doing quite well, judging by all the news that the company is releasing recently.

We can hope to see the first wave of products built using 3 nm manufacturing process sometime around end of year 2022, when the holiday season arrives. Usual customers like Apple and HiSilicon will surely utilize the new node and deliver their smartphones with 3 nm processors inside as soon as the process is ready for HVM.

TSMC vice chairman and CEO C.C. Wei announced the company's plans for 5 nm are on track, which means High Volume manufacturing (HVM) on the node is expected to be achieved by 2Q 2020. The company has increased expenditures in ramping up its various nodes from an initially projected $10 billion to something along the lines of $14 billion - 15 billion; the company is really banking on quick uptake and design wins on its most modern process technologies - and the increased demand that follows.

TSMC's 5 nm process (N5) will use extreme ultraviolet lithography (EUVL) in many more layers than its N7+ and N6 processes, with up to 14 layers being etched in the N5 silicon compared to five and six, respectively, for its "older" N7+ and N6 processes. As the company increases capital expenditure in acquiring EUVL-capable equipment that sets up its production nodes for the market they foresee will just gobble up the chips in 2020, the company is optimistic they can achieve growth in the 5-10% number.

"Moore's Law" is a term coined in 1965 by Gordon Moore, who presented a paper which predicts that semiconductor scaling will allow integrated circuits to feature twice as many transistors present per same area as opposed to a chip manufactured two years ago. That means we could get same performance at half the power than the previous chip, or double the performance at same power/price in only two years time. Today we'll investigate if Moore's Law stayed true to its cause over the years and how much longer can it keep going.

According to industry sources over at DigiTimes, TSMC will begin mass production of its 5 nm node in March 2020, when companies using the 5 nm PDK can tape out their designs and integrate them into future products. Going into volume production two years after the 7 nm node, 5 nm is trying to put Moore's Law back on track again.

Built using the Extreme Ultra-Violet lithography (also known as EUV), 5 nm node is supposed to utilize existing FinFET transistors along with many improvements in speed, power and density when compared to existing 7 nm node. Speed is supposed to increase by around 15%, while density will improve by as much as 80%, which is excellent news for everyone. Noticeable power reduction is also present and it is now possible to have about 30% reduction in power consumption, while also enjoying additional speed and density improvements that new node brings.

Intel's semiconductor manufacturing business has had a terrible past 5 years as it struggled to execute its 10 nanometer roadmap forcing the company's processor designers to re-hash the "Skylake" microarchitecture for 5 generations of Core processors, including the upcoming "Comet Lake." Its truly next-generation microarchitecture, codenamed "Ice Lake," which features a new CPU core design called "Sunny Cove," comes out toward the end of 2019, with desktop rollouts expected 2020. It turns out that the 10 nm process it's designed for, will have a rather short reign at Intel's fabs. Speaking at an investor's summit on Wednesday, Intel put out its silicon fabrication roadmap that sees an accelerated roll-out of Intel's own 7 nm process.

When it goes live and fit for mass production some time in 2021, Intel's 7 nm process will be a staggering 3 years behind TSMC, which fired up its 7 nm node in 2018. AMD is already mass-producing CPUs and GPUs on this node. Unlike TSMC, Intel will implement EUV (extreme ultraviolet) lithography straightaway. TSMC began 7 nm with DUV (deep ultraviolet) in 2018, and its EUV node went live in March. Samsung's 7 nm EUV node went up last October. Intel's roadmap doesn't show a leap from its current 10 nm node to 7 nm EUV, though. Intel will refine the 10 nm node to squeeze out energy-efficiency, with a refreshed 10 nm+ node that goes live some time in 2020.

Intel's Xe discrete GPU project head Raja Koduri recently visited a Samsung Electronics silicon fabrication facility in Korea at the backdrop of the company's major 5 nm EUV announcement. This sparks speculation that Koduri could be exploring Samsung's portfolio of sub-10 nm contract-manufacturing offerings to mass-produce Xe discrete GPUs. Intel's own foundry business is reeling with mounting pressure from the company's main breadwinner, the client and enterprise processor businesses, to get its 10 nm node on the road. Koduri's GPU would need to leverage higher transistor densities than what Intel's 10 nm could offer, given that rival AMD is already implementing 7 nm, and NVIDIA is expected to go sub-10 nm with its future generation of GPUs.

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today announced that its 5-nanometer (nm) FinFET process technology is complete in its development and is now ready for customers' samples. By adding another cutting-edge node to its extreme ultraviolet (EUV)-based process offerings, Samsung is proving once again its leadership in the advanced foundry market.

Compared to 7 nm, Samsung's 5 nm FinFET process technology provides up to a 25 percent increase in logic area efficiency with 20 percent lower power consumption or 10 percent higher performance as a result of process improvement to enable us to have more innovative standard cell architecture. In addition to power performance area (PPA) improvements from 7 nm to 5 nm, customers can fully leverage Samsung's highly sophisticated EUV technology. Like its predecessor, 5 nm uses EUV lithography in metal layer patterning and reduces mask layers while providing better fidelity.