Demand in the global foundry market remains strong in 1Q21, according to TrendForce's latest investigations. As various end-products continue to generate high demand for chips, clients of foundries in turn stepped up their procurement activities, which subsequently led to a persistent shortage of production capacities across the foundry industry. TrendForce therefore expects foundries to continue posting strong financial performances in 1Q21, with a 20% YoY growth in the combined revenues of the top 10 foundries, while TSMC, Samsung, and UMC rank as the top three in terms of market share. However, the future reallocation of foundry capacities still remains to be seen, since the industry-wide effort to accelerate the production of automotive chips may indirectly impair the production and lead times of chips for consumer electronics and industrial applications.

TSMC has been maintaining a steady volume of wafer inputs at its 5 nm node, and these wafer inputs are projected to account for 20% of the company's revenue. On the other hand, owing to chip orders from AMD, Nvidia, Qualcomm, and MediaTek, demand for TSMC's 7 nm node is likewise strong and likely to account for 30% of TSMC's revenue, a slight increase from the previous quarter. On the whole, TSMC's revenue is expected to undergo a 25% increase YoY in 1Q21 and set a new high on the back of surging demand for 5G, HPC, and automotive applications.

TSMC is one of the world's biggest semiconductor manufacturers, and the company is currently the leading provider of the newest technologies like 5 nm and 3 nm, along with advanced packaging. So far, TSMC's biggest customers have included Apple, NVIDIA, AMD, etc., where the company has mainly produced chips for mobile phones and PCs/Servers. However, Taiwan's Economics Ministry has announced that they have spoken to TSMC and have reached an agreement that the company will be putting away some additional capacity for the automotive industry, specifically for the production of automotive chips. The reason for this push is the increasing shortage of semiconductors for automakers, experienced due to the Trump administration sanctions against key Chinese chip factories.

TSMC has stated that "Other than continuously maximizing utilization of our existing capacity, Dr. Wei also confirmed in our investors' conference that we are working with customers closely and moving some of their mature nodes to more advanced nodes, where we have a better capacity to support them". The company also states that their capacities are fully utilized for now, however, TSMC has ensured ministry that "if production can be increased by optimizing production capacity, it will cooperate with the government to regard automotive chips as a primary application." That means that TSMC will not decrease any existing capacity, but rather just evaluate any increased capacity for automotive chip production.

Research and development spending by semiconductor companies worldwide is forecast to grow 4% in 2021 to $71.4 billion after rising 5% in 2020 to a record high of $68.4 billion, according to IC Insights' new 2021 edition of The McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry. Total R&D spending by semiconductor companies is expected to rise by a compound annual growth rate (CAGR) of 5.8% between 2021 and 2025 to $89.3 billion.

When the world was hit by the Covid-19 virus health crisis in 2020, wary semiconductor suppliers kept a lid on R&D spending increases, even though total semiconductor industry revenue grew by a surprising 8% in the year despite the economic fallout from the deadly pandemic. Semiconductor R&D expenditures as a percentage of worldwide industry sales slipped to 14.2% in 2020 compared to 14.6% in 2019, when research and development spending declined 1% and total semiconductor revenue fell 12%. Figure 1 plots semiconductor R&D spending levels and the spending-to-sales ratios over the past two decades and IC Insights' forecast through 2025.

AMD is always in development mode and just when they launch a new product, the company is always gearing up for the next-generation of devices. Just a few months ago, back in November, AMD has launched its Zen 3 core, and today we get to hear about the next steps that the company is taking to stay competitive and grow its product portfolio. In the AnandTech interview with Dr. Lisa Su, and The Street interview with Rick Bergman, the EVP of AMD's Computing and Graphics Business Group, we have gathered information about AMD's plans for Zen 4 core development and RDNA 3 performance target.

Starting with Zen 4, AMD plans to migrate to the AM5 platform, bringing the new DDR5 and USB 4.0 protocols. The current aim of Zen 4 is to be extremely competitive among competing products and to bring many IPC improvements. Just like Zen 3 used many small advances in cache structures, branch prediction, and pipelines, Zen 4 is aiming to achieve a similar thing with its debut. The state of x86 architecture offers little room for improvement, however, when the advancement is done in many places it adds up quite well, as we could see with 19% IPC improvement of Zen 3 over the previous generation Zen 2 core. As the new core will use TSMC's advanced 5 nm process, there is a possibility to have even more cores found inside CCX/CCD complexes. We are expecting to see Zen 4 sometime close to the end of 2021.

According to a market analysis from TrendForce, Intel's manufacturing efforts with TSMC will go way beyond a potential TSMC technology licensing for that company's manufacturing technology to be employed in Intel's own fabs. The market research firm says that Intel will instead procure wafers directly from TSMC, starting on 2H2021, in the order of 20-25% of total production for some of its non-CPU products. But the manufacturing deal is said to go beyond that, with TSMC picking up orders for Intel's Core i3 CPUs in the company's 5 nm manufacturing node - one that Intel will take years to scale down to on its own manufacturing capabilities.

According to TrendForce, that effort will scale upwards with TSMC manufacturing certain allotments of Intel's midrange and high-end CPUs using the semiconductor manufacturer's 3 nm technology in 2022. TrendForce believes that increased outsourcing of Intel's product lines will allow the company to not only continue its existence as a major IDM, but also maintain and prioritize in-house production lines for chips with high margins, while more effectively spending CAPEX on advanced R&D due to savings on fabrication technology scaling - fewer in-house chips means lower needs for investment in capacity increases, which would allow the company to sink the savings into further R&D. The move would also allow Intel to close the gap with rival AMD's manufacturing advantages in a more critical, timely manner.

When Apple first announced the M1, questions arose about the differences between it and the A14 chip which both share many architectural features and are both manufactured on TSMC's 5 nm process. Semiconductor analysis firm TechInsights has recently published die photos of the two processors and a summary of the changes.

The M1 features four high-performance Firestorm cores and four energy-efficient IceStorm cores for a total of eight CPU cores. The A14 only features six CPU cores with two high-performance Firestorm cores and four energy-efficient IceStorm cores. The M1 includes doubles the amount of GPU cores and DDR interfaces then found on the A14. The M1 also incorporates silicon not found on the A14 including the Apple T2 security processor and other controllers. These additions result in a die size 37% larger than the A14.

The rumor mill has begun grinding with details about NVIDIA's next-gen graphics processors based on the "Lovelace" architecture, with Kopite7kimi (a reliable source with NVIDIA leaks) predicting a 71% increase in shader units for the "AD102" GPU that succeeds the "GA102," with 12 GPCs holding 6 TPCs (12 SMs), each. 3DCenter.org extrapolates on this to predict a CUDA core count of 18.432 spread across 144 streaming multiprocessors, which at a theoretical 1.80 GHz core clock could put out an FP32 compute throughput of around 66 TFLOP/s.

The timing of this leak is interesting, as it's only 3 months into the market cycle of "Ampere." NVIDIA appears unsettled with AMD RDNA2 being competitive with "Ampere" at the enthusiast segment, and is probably bringing in its successor, "Lovelace" (after Ada Lovelace), out sooner than expected. Its previous generation "Turing" architecture saw market presence for close to two years. "Lovelace" could leverage the 5 nm silicon fabrication process and its significantly higher transistor density, to step up performance.

NVIDIA has launched its GeForce RTX 3000 series of graphics cards based on the Ampere architecture three months ago. However, we are already getting information about the next-generation that the company plans to introduce. In the past, the rumors made us believe that the architecture coming after Ampere is allegedly being called Hopper. Hopper architecture is supposed to bring multi-chip packaging technology and be introduced after Ampere. However, thanks to @kopite7kimi on Twitter, a reliable source of information, we have data that NVIDIA is reportedly working on a monolithic GPU architecture that the company internally refers to as "ADxxx" for its codenames.

The new monolithically-designed Lovelace architecture is going make a debut on the 5 nm semiconductor manufacturing process, a whole year earlier than Hopper. It is unknown which foundry will manufacture the GPUs, however, both of NVIDIA's partners, TSMC and Samsung, are capable of manufacturing it. The Hopper is expected to arrive sometime in 2023-2024 and utilize the MCM technology, while the Lovelace architecture will appear in 2021-2022. We are not sure if the Hopper architecture will be exclusive to data centers or extend to the gaming segment as well. The Ada Lovelace architecture is supposedly going to be a gaming GPU family. Ada Lovelace, a British mathematician, has appeared on NVIDIA's 2018 GTC t-shirt known as "Company of Heroes", so NVIDIA may have already been using the ADxxx codenames internally for a long time now.

Taiwan Semiconductor Manufacturing Company (TSMC), one of the largest semiconductor manufacturers in the world, is reportedly ending its volume discounts. The company is the maker of the currently smallest manufacturing nodes, like 7 nm and 5 nm. For its biggest customers, TSMC used to offer a discount - when you purchase 10s or 100s of thousands of 300 mm (12-inch) wafers per month, the company will give you a deal of a 3% price decrease per wafer, meaning that the customer is taking a higher margin off a product it sells. Many of the customers, like Apple, NVIDIA, and AMD, were a part of this deal.

Today, thanks to a report from the Taiwanese Central News Agency, TSMC is terminating this type of discount. Now, every customer will pay full price for the wafer, without any exceptions. For now, it is unclear what drove that decision at TSMC's headquarters, but the only thing that we could think is that the demand is too high to keep up with the discounts and the margins are possibly lower. What this means for consumers is a possible price increase in products that are manufactured at TSMC's facilities. The consumer market is already at a drought of new PC components like CPUs and GPUs due to high demand and scalping. This could contribute a bit to the issue, however, we do not expect it to be of any major significance.

They say that it is hard to keep up with Moore's Law, however, for the folks over at Taiwan Semiconductor Manufacturing Company (TSMC), that doesn't seem to represent any kind of a problem. Today, to confirm that TSMC is one of the last warriors for the life of Moore's Law, we have information that the company has completed building its manufacturing facility for the next-generation 3 nm semiconductor node. Located in Southern Taiwan Science Park near Tainan, TSMC is expecting to start high-volume manufacturing of the 3 nm node in that Fab in the second half of 2022. As always, one of the first customers expected is Apple.

Estimated to cost an amazing 19.5 billion US Dollars, the Fab is expected to have an output of 55,000 300 mm (12-inch) wafers per month. Given that the regular facilities of TSMC exceed the capacity of over 100K wafers per month, this new facility is expected to increase the capacity over time and possibly reach the 100K level. The new 3 nm node is going to use the FinFET technology and will deliver a 15% performance gain over the previous 5 nm node, with 30% decreased power use and up to 70% density increase. Of course, all of those factors will depend on a specific design.

Marvell today unveiled the industry's first 112G 5 nm SerDes solution that has been validated in hardware. The DSP-based SerDes boasts industry-leading performance, power and area, helping to propel 112G as the interconnect of choice for next generation 5G, enterprise, and cloud data center infrastructure. Marvell has recently secured a new custom ASIC design win customer that will embed this new IP to build next generation top-of-rack (ToR) and spine switches for leading hyperscale data centers around the world. The Marvell 5 nm SerDes solution doubles the bandwidth of current systems based on 56G while enabling the deployment of 112G I/Os in many exciting new applications, including network and data center switching, network traffic management, machine learning training and inference, and application-specific accelerators.

Today's news, which comes on the heels of the company's announcement with TSMC of its 5 nm portfolio, further strengthens Marvell's leading data infrastructure offerings in the industry's most advanced process geometry. The 112G 5 nm SerDes solution is part of Marvell's industry-leading IP portfolio that addresses the full spectrum of infrastructure requirements and includes processor subsystems, encryption engines, system-on-chip fabrics, chip-to-chip interconnects, and a variety of physical layer interfaces.

Apple has recently announced its transition to Apple Silicon, meaning that every processor inside its products will be custom designed by the company. However, that seems to be becoming a bit of a problem. The sole supplier of chips for Apple has been Taiwan Semiconductor Manufacturing Company (TSMC), which Apple collaborated with for the past few years. The sheer capacity of TSMC is enough to satisfy the demand from several companies and thus it allows some of them to book its capacity. With Apple demanding more and more capacity than ever before, it is becoming quite hard to keep up with it. That is why Apple is, according to some analysts for Business Korea, looking for a foundry beyond TSMC's to manufacture its chips.

According to the source, Apple is looking at the direction of Samsung Electronics and its silicon manufacturing facilities. Samsung has recently started the production of its 5 nm silicon manufacturing node. We have reported that the first SoCs are set to arrive soon. However, it may be possible that Apple's M1 lineup of SoCs will be a part of that first wave. Apple is reportedly going to tap both TSMC and Samsung to qualify enough supply for the huge demand of the products based on the latest 5 nm technology.

During its Q3 earnings call, Samsung Electronics has provided everyone with an update on its foundry and node production development. In the past year or so, Samsung's foundry has been a producer of a 7 nm LPP (Low Power Performance) node as its smallest node. That is now changed as Samsung has started the production of the 5 nm LPE (Low Power Early) semiconductor manufacturing node. In the past, we have reported that the company struggled with yields of its 5 nm process, however, that seems to be ironed out and now the node is in full production. To contribute to the statement that the new node is doing well, we also recently reported that Samsung will be the sole manufacturer of Qualcomm Snapdragon 875 5G SoC.

The new 5 nm semiconductor node is a marginal improvement over the past 7 nm node. It features a 10% performance improvement that is taking the same power and chip complexity or a 20% power reduction of the same processor clocks and design. When it comes to density, the company advertises the node with x1.33 times increase in transistor density compared to the previous node. The 5LPE node is manufactured using the Extreme Ultra-Violet (EUV) methodology and its FinFET transistors feature new characteristics like Smart Difusion Break isolation, flexible contact placement, and single-fin devices for low power applications. The node is design-rule compatible with the previous 7 nm LPP node, so the existing IP can be used and manufactured on this new process. That means that this is not a brand new process but rather an enhancement. First products are set to arrive with the next generation of smartphone SoCs, like the aforementioned Qualcomm Snapdragon 875.

Apple has established itself as a master of silicon integrated circuit design and has proven over the years that its processors deliver the best results, generation after generation. If we take a look at the performance numbers of the latest A14 Bionic, you can conclude that its performance is now rivaling some of the x86_64 chips. So you would wonder, what is inside this SoC that makes it so fast? That is exactly what ICmasters, a semiconductor reverse engineering and IP services company, has questioned and decided to find out. For starters, we know that Apple manufactures the new SoCs on TSMC's N5 5 nm node. The Taiwanese company promises to pack 171.3 million transistors per square millimeter, so how does it compare to an actual product?

ICmasters have used electron microscopy to see what the chip is made out of and to measure the transistor density. According to this source, Apple has a chip with a die size of 88 mm², which packs 11.8 billion N5 transistors. The density metric, however, doesn't correspond to that of TSMC. Instead of 171.3 million transistors per mm², the ICmasters measured 134.09 million transistors per mm². This is quite a difference, however, it is worth noting that each design will have it different due to different logic and cache layout.

Apple announced plans to transition their Mac lineup to in-house ARM-based processors earlier this year. This decision came as a result of Apple's dependence on Intel for new processors each year and their recent underwhelming improvements. The upcoming 12 core chip is expected to be manufactured on TSMC's 5 nm node which should deliver significant power savings and performance. Apple has been working to optimize macOS and first party applications for the new processors along with sending out developer transition kits to hopefully ensure major software is supported at launch. The processor is rumored to debut in an upcoming 13-inch MacBook Pro or a new MacBook Air and should launch at a dedicated event in November according to a recent report by Bloomberg.

TSMC has hit a jackpot with its newer nodes like 7 nm and now 5 nm, as the company is working with quite good yields. To boast, TSMC has seen all of its capacity of 7 nm being fully booked by customers like AMD, Apple, and NVIDIA. However, it seems like the company's next-generation 5 nm node is also getting high demand. According to the latest report from DigiTimes, TSMC's N5 5 nm node is fully booked to the end of 2020. And the biggest reason for that is the biggest company in the world - Apple. Since Apple plans to launch the next-generation iPhone, iPad, and Arm-based MacBook, the company has reportedly booked most of the 5 nm capacity for 2020, meaning that there are lots of chips that Apple will consume. TSMC can't be dependent only on one company like Apple, so the smaller portion of capacity went to other customers as well.

TSMC, one of the biggest silicon manufacturers in the world, usually doesn't disclose company pricing of the silicon it manufactures and only shares that with its customers. It appears that RetiredEngineer (@chiakokhua on Twitter) got a hold of the pricing of TSMCs wafers on every manufacturing node starting from 90 nm down to 5 nm. That includes a wide portfolio of 65, 40, 28, 20, 16/12, 10, and 7 nm nodes as well. The table shown below includes information dating to April 2020, so it is possible that some things are now different and they surely are. There are a few quite interesting notes from the image, namely the price increase as the node shrinks.

From 90 nm to 20 nm, the price of the wafer didn't increase as much, however, starting from 16/12 nm node(s), TSMC has seen costs per wafer, and other costs increase exponentially. For example, just compare the 10 nm wafer price of $5992 with the price of a 5 nm wafer which costs an amazing $16988. This is more than a 180% price increase in just three years, however, the cost per transistor is down as you get around 229% higher density in that period, making TSMC actually in line with Moore's Law. That is comparing Transistor density (MTr / mm²) of52.51 million transistors for the 10 nm node and 173 million transistors per mm² of the 5 nm node .

Rumors fresh of South Korean shores claim that Samsung has snagged a position as sole provider for Qualcomm's Snapdragon 875 SoC on its 5 nm EUV manufacturing process. The reason for this, according to a supposed industry insider, boiled down to money (as it almost always does): Samsung simply offered lower pricing for chips manufactured under its 5 nm EUV process than TSMC did. The deal has been claimed to be worth some $840M. This makes sense, as Samsung has a considerable product portfolio - including lucrative memory fabrication - from which it can pool resources so as to lower pricing for new manufacturing technologies, whereas TSMC can only count on revenues it brings in from contracted silicon manufacturing deals.

Samsung's 5 nm EUV will still offer the now tried-and-true FinFet transistor design - next-generation GAAFET (gate all-around FET) are reserved for the companies' 3 nm efforts. This piece of news directly contradicts Digitimes' earlier reporting on Qualcomm leaving Samsung as a foundry partner due to lower than adequate yields for Samsung's 5 nm EUV. With Samsung already manufacturing NVIDIA's Ampere on its 8 nm node, and now with a confirmed high-volume client with Qualcomm, this likely means more available capacity for other TSMC clients - of which we could mention AMD and Apple.

When Apple announced their transition form Intel processors to Apple Silicon, we were left wondering how the silicon will perform and what characteristics will it bring with it. According to the latest report from The China Times, the Apple custom GPU found inside the new Apple Silicon will bring better performance and energy efficiency compared to Intel iGPU it replaces. The 5 nm GPU manufactured on TSMC's N5 semiconductor manufacturing node is supposedly codenamed "Lifuka" and it brings Apple's best to the table. Planned to power a 12-inch MacBook, the GPU will be paired with a custom CPU based on Arm ISA as well. The same chips powering iPhone and iPad devices will go into MacBook devices, with the TDP increased as MacBook will probably have much higher cooling capacity. The first Apple Silicon MacBook will come in H2 of 2021.Here is the copy of a full report from The China Times below:

TSMC had been working super hard in the past few years and has been investing in lots of new technologies to drive the innovation forward. At TSMC's Technology Symposium held this week was, the company has presented various things like the update on its 12 nm node, as well as future plans for node development. One of the most interesting announcements made this week was TSMC's state and ownership of Extreme Ultra-Violet (EUV) machines. ASML, the maker of these EUV machines used to etch the pattern on silicon, has been the supplier of the Taiwanese company. TSMC has announced that they own an amazing 50% of all EUV machine installations.

What is more important is the capacity that the company achieves with it. It is reported that TSMC achieves 60% of all EUV wafer capacity in the world, which is a massive achievement of what TSMC can do with the equipment. The company right now has only two nodes on EUV in high-volume manufacturing, the 7 nm+ node and 5 nm node (which is going HVM in Q4), however, that is more than any of its competitors. All of the future nodes are to be manufactured using the EUV machines and the smaller nodes require it. As far as the competitors go, only Samsung is currently making EUV silicon on the 7 nm LPP node. Intel is yet to release some products on a 7 nm node of its own, which is the first EUV node from the company.

SiliconArts today released RC-MC, its next generation RayCore graphics architecture. The RayCore MC is scalable and modular to enable integration on a wide variety of gaming platforms including cloud, desktop, mobile, console and VR/AR. The RC-MC is being made available in an external Graphics Accelerator (eGFX) for content developers and SOC design evaluation.

Jon Peddie, principle and founder of Jon Peddie Research, says of the RayCore MC product release: "SiliconArts' latest product breaks another barrier between the professional rendering and the broader graphics market, with path tracing features such as global illumination and soft shadows that are being deployed in advanced rendering farms today."

TSMC on Monday kicked off a virtual tech symposium, where it announced its new 12 nm N12e node for IoT edge devices, announced the new 3DFabric Technology, and detailed progress on its upcoming 5 nm N5 and 3 nm N3 silicon fabrication nodes. The company maintains that the N5 (5 nm) node offers the benefits of a full node uplift over its current-gen N7 (7 nm), which recently clocked over 1 billion chips shipped. The N5 node incorporates EUV lithography more extensively than N6/N7+, and in comparison to N7 offers 30% better power at the same performance, 15% more performance at the same power, and an 80% increase in logic density. The company has commenced high-volume manufacturing on this node.

2021 will see the introduction and ramp-up of the N5P node, an enhancement of the 5 nm N5 node, offering a 10% improvement in power at the same performance, or 5% increase in performance at the same power. A nodelet of the N5 family of nodes, called N4, could see risk production in Q4 2021. The N4 node is advertised as "4 nm," although the company didn't get into its iso-power/iso-performance specifics over the N5 node. The next major node for TSMC will be the 3 nm N3 node, with massive 25%-30% improvement in power at the same performance, or 10%-15% improvement in performance at same power, compared to N5. It also offers a 70% logic density gain over N5. 3DFabric technology is a new umbrella term for TSMC's CoWoS (chip on wafer on substrate), CoW (chip on wafer), and WoW (wafer on wafer) 3-D packaging innovations, with which it plans to offer packaging innovations that compete with Intel's various new 3D chip packaging technologies on the anvil.

The Apple A14X Bionic is an upcoming processor from Apple which is expected to feature in the upcoming iPad Pro models and should be manufactured on TSMC's 5 nm node. Tech YouTuber Luke Miani has recently provided a performance graph for the A14X chip based on "leaked/suspected A14 info + average performance gains from previous X chips". In these graphs, the Apple A14X can be seen matching the Intel Core i9-9880H in Geekbench 5 with a score of 7480. The Intel Intel Core i9-9880H is a 45 W eight-core mobile CPU found in high-end notebooks such as the 2019 16-inch MacBook Pro and requires significant cooling to keep thermals under control.

If these performance estimates are correct or even close then Apple will have a serious productivity device and will serve as a strong basis for Apple's transition to custom CPU's for it's MacBook's in 2021. Apple may use a custom version of the A14X with slightly higher clocks in their upcoming ARM MacBooks according to Luke Miani. These results are estimations at best so take them with a pinch of salt until Apple officially unveils the chip.

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today announced the immediate availability of its silicon-proven 3D IC packaging technology, eXtended-Cube (X-Cube), for today's most advanced process nodes. Leveraging Samsung's through-silicon via (TSV) technology, X-Cube enables significant leaps in speed and power efficiency to help address the rigorous performance demands of next-generation applications including 5G, artificial intelligence, high-performance computing, as well as mobile and wearable.

"Samsung's new 3D integration technology ensures reliable TSV interconnections even at the cutting-edge EUV process nodes," said Moonsoo Kang, senior vice president of Foundry Market Strategy at Samsung Electronics. "We are committed to bringing more 3D IC innovation that can push the boundaries of semiconductors."

Samsung Electronics reported today KRW 52.97 trillion in consolidated revenue and KRW 8.15 trillion in operating profit for the second quarter ended June 30, 2020. Even as the spread of COVID-19 caused closures and slowdowns at stores and production sites around the world, the Company responded to challenges through its extensive global supply chain, while minimizing the impact of the pandemic by strengthening online sales channels and optimizing costs.

Quarterly operating profit rose 26 percent from the previous quarter and 23 percent from a year earlier, thanks to firm demand for memory chips and appliances, as well as a one-off gain at its Display Panel Business. A partial recovery in global demand since May also helped offset some COVID-19 effects, resulting in higher earnings than initially expected. Revenue in the quarter fell 4 percent from the previous quarter and 6 percent from a year earlier due to reduced sales of smartphones and other devices.