AleksandarKso the smaller portion of capacity went to other customers as well.

Namely ~ AMD, among others?

Was AMD planning anything on 5nm in 2021? Ryzen 4 perhaps?

R0H1TNamely ~ AMD, among others?

I don't know surely so won't speculate.

ratirtWas AMD planning anything on 5nm in 2021? Ryzen 4 perhaps?

AMD's definitely on track for 5nm zen4 so we should likely see it in servers or even desktops before the end of next year. Of course we'll also have to see the impact of nCoV & how the global economy does by then. Then there's Intel ~ if they can stick to their "revised" roadmap for 7nm then AMD will have to bring out their best on time next year. They simply can't afford to sit back, like they did when Conroe virtually blindsided them!

I believe AMD will only start utilizing 5nm in 2021 so that the products will be available in 2022. Not surprising Apple will book out 5nm for the rest of the year because they are ramping up their A14 SOC for iPhones, iPads, Macbook, etc...

AleksandarKI don't know surely so won't speculate.

It is a possibility.

5 Oct 2018: community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/tsmc-oip-report?pifragment-1779=2
"N5 is ready for design starts. EDA V0.5 certification is done, with V0.9 ongoing (to be complete in November). Foundation IP (standard cells, SRAM, GPIO, eFuse) all have early silicon validation results."

AMD MTS - Sep 2018 – Present
2 years. Hyderabad Area, India. FEINT. Synthesis over 7nm/5nm

"1 year ago" => R&D Engineer, II
Tools: Hsim/ Hspice/ Schematic Capture/ Extraction/ Verilog/Unix
Project/ comments: N5 for Hi Silicon and AMD
N5 for Hi Silicon and AMD
Requirements => Basic know how of SRAM, ROM circuits

Which appears again:
N5 TSMC FINFET, HDSP, UHD2PRF and HDRF2P Testchip and compiler development from scratch for Hi-Silicon and AMD @Synopsys

2013-2018 profile: L2 Macro -5nm FinFET Test Chip Layout
May 2019 - August 2019 profile: Supported L3 Cache Physical Design team -Worked with the TSMC 7nm and 5nm

October 2018 => October 2020 is well within the timeframe given EUV's speed over DUV.



www.dolphin-ic.com/products/standard-cell/tsmc_5ff_cell.html

• 6-track, Ultra High Density (51nm and 57nm poly pitch)

www.dolphin-ic.com/products/standard-cell/tsmc_7ff+_cell.html

• 6-track, Ultra High Density (57nm poly pitch)

5nm's 57nm poly-pitch might support retapeouts of 7nm+'s 57nm poly pitch.

Timeframe from Matisse/Rome sampling in 2018; one year after risk production of 7nm DUV. Coincides, with the timeframe of Milan/Vermeer A0&B0 sampling in 2020; also one year after risk production of 5nm EUV.

Ex:
hardforum.com/threads/the-radeon-technology-group-rtg-has-received-its-first-zen-2-sample.1967802/
Which is pretty close to => www.amd.com/en/products/cpu/amd-ryzen-7-3800x

This is sort of misleading, Apple needs the low power variants of these nodes, so the wafers they bought don't overlap with what AMD, Nvidia and others need for stuff like desktop chips/HPC/etc.

Vya DomusThis is sort of misleading, Apple needs the low power variants of these nodes, so the wafers they bought don't overlap with what AMD, Nvidia and others need for stuff like desktop chips/HPC/etc.

I think it has to do something with production capacity. 5nm low power is being made on the same factory line as high performance. They split the time needed for the end product. TSMC knows the capacity they can produce in a time frame. You just apply for the time TSMC needs to make those. Apple got most of the time required for 5nm wafers with low power option. The rest will probably go to AMD.

ratirtWas AMD planning anything on 5nm in 2021? Ryzen 4 perhaps?

RDNA 3

N5 Q1+ 2020 shipments => AMD, Apple, Hisilicon(b4b), Bitmain (Phase 1 customers)
N5 Q1+ 2021 shipments => Mediatek, Nvidia, Qualcomm, Intel (Phase 2 customers)

There is multiple rumors but AMD is the one buying most of N5.
Apple rumor => 45,000 wafers per quarter.
AMD rumor => 60,000 wafers per quarter, till 4Q20 onwards which it is upgraded to 90,000 wafers. (Q4+ is N5 pdk 1.1 aka N5P)
Based on price rumors that is only ~320+ million USD per quarter.
Which is well within AMD's operating expenses => www.macrotrends.net/stocks/charts/AMD/amd/operating-expenses

It isn't the first time they paid that much anyway.
techreport.com/news/24026/amd-lowers-wafer-orders-will-pay-320-million-charge/
www.anandtech.com/show/10631/amd-amends-globalfoundries-wafer-supply-agreement-through-2020



TSMC also buys AMD's CPU/GPU products, so there might be a discount for AMD. Do to the symbiotic bond they have now.

chief-gunneyRDNA 3

That & CDNA (2?) IIRC.

seronxTSMC also buys AMD's CPU/GPU products, so there might be a discount for AMD. Do to the symbiotic bond they have now.

I doubt TSMC is buying $320 million of AMD's products, though...

AssimilatorI doubt TSMC is buying $320 million of AMD's products, though...

Why would they AMD is selling. Unless, the intent is do as Japan and buy 5nm products and sell them at a loss. That amount of commitment implicates that TSMC might as well just buy AMD.

seronxN5 Q1+ 2020 shipments => AMD, Apple, Hisilicon(b4b), Bitmain (Phase 1 customers)

Yeah, no Hisilicon, they've been banned from producing with TSMC.

and NVIDIA ... ???? WHAT?

TheLostSwedeYeah, no Hisilicon, they've been banned from producing with TSMC.

b4b = Be Fore Ban, btw. Hi1630 and Kirin 1000/1020 is still planned to launch. So, they retrieved their orders sometime ago.

PerfectWaveand NVIDIA ... ???? WHAT?

GA100 826 mm2 => rumor mill it is HOGGING all the wafers!

TheLostSwedeYeah, no Hisilicon, they've been banned from producing with TSMC.

Have they?

Huawei reportedly has only 8.8 million Kirin 9000 chipsets for the Mate 40 smartphones

The 5nm wafer can yield about 400 dies, and TSMC has about 22k wafers.

I just can't see why AMD would need 5nm capacity in Q3 of 2020 when we will be very lucky if we see Zen 4 or RDNA 3 even in 2021, so we are talking about a year and half until AMD releases a 5nm part with current expected roadmaps.
My money would be on a 3090 killer at some point on 5nm but still RDNA 2 based and also I believe AMD have delay Zen 4 well into 2022 and we will get Zen 3+. AMD pretty much said this with their mobo support list.

R0H1THave they?

Huawei reportedly has only 8.8 million Kirin 9000 chipsets for the Mate 40 smartphones

The 5nm wafer can yield about 400 dies, and TSMC has about 22k wafers.

From memory all orders needed to be completed before October and then the US is deciding for the world which phones we are allowed to buy.

pjl321I just can't see why AMD would need 5nm capacity in Q3 of 2020

www.techpowerup.com/forums/threads/rumor-next-gen-nvidia-rtx-chip-will-be-based-on-samsung-10nm-node.264711/#post-4224340
A100/7nm => 6912
GA102/8nm => 10496
Similar source as the above.

AMD got 5nm HVM in Q1 2020. It has been rumored that at least Zen3 and MI100 are 5nm products.

MI100 is the first 5nm product.
Zen3 is the second 5nm product. <== ((Milan-Genesis)00h-derivied dies are N5 and (Trento-Badami)30h-derivied dies are N5P)
Navi31 has replaced Navi21 and will be RDNA2 not RDNA3. 1H of 2021 availability. <== Third 5nm part and is N5P.
GFX1050 => Navi31
GFX1100 => RDNA3/Navi41

seronxwww.techpowerup.com/forums/threads/rumor-next-gen-nvidia-rtx-chip-will-be-based-on-samsung-10nm-node.264711/#post-4224340
A100/7nm => 6912
GA102/8nm => 10496
Similar source as the above.

AMD got 5nm HVM in Q1 2020. It has been rumored that at least Zen3 and MI100 are 5nm products.

MI100 is the first 5nm product.
Zen3 is the second 5nm product.
Navi31 has replaced Navi21 and will be RDNA2 not RDNA3. 1H of 2021 availability.
GFX1050 => Navi31
GFX1100 => RDNA3/Navi41

I could believe AMD has a CDNA card on 5nm soonish, and maybe a high end RDNA2 on 5nm at some point in 2021. But I really can't get on board that Zen 3 is 5nm as we have just seen too much of it for that to be the case. As I said I think the most likely option is Zen 3+ refresh using 5nm next year as Zen 4 has been pushed back into 2022.

seronxwww.techpowerup.com/forums/threads/rumor-next-gen-nvidia-rtx-chip-will-be-based-on-samsung-10nm-node.264711/#post-4224340
A100/7nm => 6912
GA102/8nm => 10496
Similar source as the above.

AMD got 5nm HVM in Q1 2020. It has been rumored that at least Zen3 and MI100 are 5nm products.

MI100 is the first 5nm product.
Zen3 is the second 5nm product. <== ((Milan-Genesis)00h-derivied dies are N5 and (Trento-Badami)30h-derivied dies are N5P)
Navi31 has replaced Navi21 and will be RDNA2 not RDNA3. 1H of 2021 availability. <== Third 5nm part and is N5P.
GFX1050 => Navi31
GFX1100 => RDNA3/Navi41

I don't think this is correct. The Zen 3 aka 4000 series will definitely be 7nm/7nm+. The Zen 4 aka 5000 series might be 5nm

Found this on WCCFTech site

ratirtI don't think this is correct. The Zen 3 aka 4000 series will definitely be 7nm/7nm+. The Zen 4 aka 5000 series might be 5nm

It's pretty much confirmed that Zen 3 will be called the 5000 series which I personally think makes sense as they should never have called Zen+ the 2000 series.
But I am also fairly sure we will see Zen 3+ which will be on 5nm because we see Zen 4.

pjl321It's pretty much confirmed that Zen 3 will be called the 5000 series which I personally think makes sense as they should never have called Zen+ the 2000 series.
But I am also fairly sure we will see Zen 3+ which will be on 5nm because we see Zen 4.

Yeah :) You are right. damn this series versus gen are so damn confusing now. :/

pjl321But I really can't get on board that Zen 3 is 5nm as we have just seen too much of it for that to be the case.

It is a bit weird, but there is a bit of nuance.

All 7nm+ products are on 5nm.

It all started with a codename list on an AMD profile
7nm/6nm/5nm Renoir/Durango/Rembrandt

Renoir is an APU that has launched
Durango is a name of a city like Bixby/Promontory.
Rembrandt is an APU and it is beside the 5nm.


Rembrandt being 5nm, means Zen3 is on 5nm. Hence, everything 7nm+ is actually 5nm.
Because Rembrandt is 5nm, Cezanne being a later model is also 5nm. Cezanne being 5nm means earlier Zen3 parts are also 5nm.

Which lead to this:
www.dolphin-ic.com/products/standard-cell/tsmc_5ff_cell.html

• 6-track, Ultra High Density (51nm and 57nm poly pitch)

www.dolphin-ic.com/products/standard-cell/tsmc_7ff+_cell.html

• 6-track, Ultra High Density (57nm poly pitch)

5nm's 57nm poly-pitch might support retapeouts of 7nm+'s 57nm poly pitch.
// Think 14LPP to 12LP or N7 to N6, but N5 does it with N7+.

I believe 7nm+ at Fab 15 is ~10K to ~30K wafer starts currently, there is no demand for it.
While 5nm at Fab 18 in January was 50K wafer starts and March was 80K wafer starts.

We can see literally two fabs(phase 1 & phase 2 of F18A) running on google maps;

seronxIt is a bit weird, but there is a bit of nuance.

All 7nm+ products are on 5nm.

It all started with a codename list on an AMD profile
7nm/6nm/5nm Renoir/Durango/Rembrandt

Renoir is an APU that has launched
Durango is a name of a city like Bixby/Promontory.
Rembrandt is an APU and it is beside the 5nm.

https://twitter.com/i/web/status/1279873180862230528

https://twitter.com/i/web/status/1296657335671230464

https://twitter.com/i/web/status/1291982462818619392

https://twitter.com/i/web/status/1199932690482499585

Rembrandt being 5nm, means Zen3 is on 5nm. Hence, everything 7nm+ is actually 5nm.
Because Rembrandt is 5nm, Cezanne being a later model is also 5nm. Cezanne being 5nm means earlier Zen3 parts are also 5nm.

Which lead to this:
www.dolphin-ic.com/products/standard-cell/tsmc_5ff_cell.html

• 6-track, Ultra High Density (51nm and 57nm poly pitch)

www.dolphin-ic.com/products/standard-cell/tsmc_7ff+_cell.html

• 6-track, Ultra High Density (57nm poly pitch)

5nm's 57nm poly-pitch might support retapeouts of 7nm+'s 57nm poly pitch.

I believe 7nm+ at Fab 15 is ~10K to ~30K wafer starts currently, there is no demand for it.
While 5nm at Fab 18 in January was 50K wafer starts and March was 80K wafer starts.

We can see literally two fabs running on google maps;

Well I really hope you are right as that would be 'epyc'!
I worry that TSMC wouldn't be able to keep up though as the EUV process takes a fair bit longer to complete even though it's simpler with less masking but the power requirements are pretty huge.
Also, this decision will have had to of been made a long time ago because TSMC's 7nm EUV process is not compatible with their 5nm EUV process, so everything will have had to of been designed for 5nm from the start and at that point HiSilicon would have been a massive partner of TSMC and so there wouldn't have been any capacity on 5nm for AMD to use.