AMD late Tuesday released its Q2-2020 financial results, which saw the company rake in revenue of $1.93 billion for the quarter, and clock a 26 percent YoY revenue growth. In both its corporate presentation targeted at the financial analysts, and its post-results conference call, AMD revealed a handful interesting bits looking into the near future. Much of the focus of AMD's presentation was in reassuring investors that [unlike Intel] it is promising a stable and predictable roadmap, that nothing has changed on its roadmap, and that it intends to execute everything on time. "Over the past couple of quarters what we've seen is that they see our performance/capability. You can count on us for a consistent roadmap. Milan point important for us, will ensure it ships later this year. Already started engaging people on Zen4/5nm. We feel customers are very open. We feel well positioned," said president and CEO Dr Lisa Su.

For starters, there was yet another confirmation from the CEO that the company will launch the "Zen 3" CPU microarchitecture across both the consumer and data-center segments before year-end, which means both Ryzen and EPYC "Milan" products based on "Zen 3." Also confirmed was the introduction of the RDNA2 graphics architecture across consumer graphics segments, and the debut of the CDNA scalar compute architecture. The company started shipping semi-custom SoCs to both Microsoft and Sony, so they could manufacture their next-generation Xbox Series X and PlayStation 5 game consoles in volumes for the Holiday shopping season. Semi-custom shipments could contribute big to the company's Q3-2020 earnings. CDNA won't play a big role in 2020 for AMD, but there will be more opportunities for the datacenter GPU lineup in 2021, according to the company. CDNA2 debuts next year.

Marvell today announced a unique custom ASIC offering that addresses the stringent requirements of next generation 5G carriers, cloud data centers, enterprise and automotive applications. Marvell's comprehensive custom ASIC solution enables a multitude of customization options and a differentiated approach with best-in-class standard product IP including Arm -based processors, embedded memories, high-speed SerDes, networking, security and a wide range of storage controller and accelerators in 5 nm and beyond. By partnering with Marvell, customers gain enhanced performance, power and area resulting in accelerated time-to-market and providing optimal returns on investment.

Traditionally, data infrastructure manufacturers and cloud data center operators have had to choose between securing standard products or a full custom silicon solution designed in-house, while developing or licensing foundational IP as needed. Now, for the first time, Marvell is offering full access to its broad and growing portfolio of industry-leading data infrastructure standard product IP and technologies, which can be integrated and enabled in custom ASIC solutions at the most advanced technology nodes.

Semiconductor manufacturing is a difficult process. Often when a new node is being developed, there are new materials introduced that may cause some yield issues. Or perhaps with 7 nm and below nodes, they are quite difficult to manufacture due to their size, as the transistor can get damaged by the smallest impurity in silicon. So manufacturers have to be extra careful and must spend more time on the development of new nodes. According to industry sources over at DigiTimes, we have information that Samsung is struggling with its 5 nm EUV node.

This unfortunate news comes after the industry sources of DigiTimes reported that Qualcomm's next-generation 5G chipsets could be affected if Samsung doesn't improve its yields. While there are no specific pieces of information on what is the main cause of bad yields, there could be a plethora of reasons. From anything related to manufacturing equipment to silicon impurities. We don't know yet. We hope that Samsung can sort out these issues in time, so Qualcomm wouldn't need to reserve its orders at rival foundries and port the design to a new process.

Taiwan Semiconductor Manufacturing Company, called TSMC shorty, has just become the world's biggest semiconductor company. The news broke after TSMC's stock reached a peak heights of $66.40 price per share, and market capitalization of 313 billion US dollars. That means that the Taiwanese company officially passed Intel, NVIDIA, and Samsung in terms of market capitalization, which is no small feat. And the news isn't that surprising. TSMC has been rather busy with orders from customers, just waiting for new spots so they can grab a piece of its production pipeline.

TrendForce, a market intelligence provider, estimates that TSMC has an amazing 51.9% of global semiconductor foundry share alone. That is no small feat but TSMC worked hard over the years to make it happen. With constant investments into R&D, TSMC has managed to make itself not only competitive with other foundries, but rather an industry leader. With 5 nm already going in high-volume manufacturing (HVM) in Q4 of this year, the company is demonstrating that it is the market leader with the latest node developments. Smaller nodes like 3 nm are already in development and TSMC doesn't plan to stop.

Apple has recently announced its transition from Intel-based Mac computers to custom Arm-based Apple silicon equipped Macs. The speculations for such transition have lasted a few years and we finally got that confirmation. So the question remains: who will manufacture Apple's custom processors for Arm-based Macs? The answer is pretty simple. It is TSMC who will again become Apple's main supplier of silicon. With its broad offerings of the latest silicon nodes, it was no brainer choice for Apple. Combined with the history of collaboration with Apple, TSMC was the only choice for new Apple silicon. Whatever the company will use the new 5 nm node or use the "old" 7 nm one, the question remains.

TSMC expects to see huge orders from Apple in the second half of 2021, for Apple silicon, so Apple will become perhaps the biggest customer of TSMC. It is also worth pointing out that Apple will be using ASMedia's USB controller for Arm-based Macs, as the original report suggests.

TSMC is reportedly planning a stopgap between its 5 nm-class silicon fabrication nodes, and the 3 nm-class, called N4. According to the foundry's CEO, Liu Deyin, speaking at a shareholders meeting, N4 will be a 4 nm node, and an enhancement of N5P, the company's most advanced 5 nm-class node. N4 is slated for mass-production of contracted products in 2023, and could help TSMC's customers execute their product roadmaps of the time. From the looks of it, N4 is a repeat of the N6 story: a nodelet that's an enhancement of N7+, the company's most advanced 7 nm-class node that leverages EUV lithography.

TSMC, the world's leading semiconductor manufacturing company, has reportedly started to accelerate research and development (R&D) of its next-generation 2 nm node. Having just recently announced that they will be starting production of a 5 nm process in Q4 of 2020, TSMC is pumping out nodes very fast and much faster compared to competition like Intel and Samsung. Having an R&D budget of almost 16 billion USD, TSMC seems to be spending the funds very wisely. The 5 nm node is going into volume production this year, and smaller nodes are already being prepared.

The 3 nm node is going into trial production in the first half of 2021, while the mass production is supposed to commence in 2022. As far as the 2 nm node, TSMC has recently purchased more expensive Extreme Ultra-Violet (EUV) lithography machines for the 2 nm node. Due to the high costs of these EUV machines, TSMC's capital spending will not be revisited this year and it should remain in the $16 billion range. As far as a timeline for 2 nm is concerned, we don't know when will TSMC start trial production as the node is still in development phases.

ASML Holding NV (ASML) today announced that it has completed system integration and testing of its first-generation HMI multibeam inspection (MBI) system for 5 nm nodes and beyond. The HMI eScan1000 demonstrated successful multibeam operation, simultaneously scanning nine beams on a number of test wafers. With nine beams, the eScan1000 will increase throughput up to 600% compared to single e-beam inspection tools for targeted in-line defect inspection applications.

The new MBI system includes an electron optics system capable of creating and controlling multiple primary electron beamlets and then collecting and processing the resulting secondary electron beams, limiting beam-to-beam crosstalk to less than 2% and delivering consistent imaging quality. It also features a high-speed stage to increase the system's overall throughput and a high-speed computational architecture to process the streams of data from the multiple beamlets in real time.

Last year Samsung and AMD announced their collaboration which promises to deliver smartphone chips with AMD RDNA 2 graphics at its heart. This collaboration is set to deliver first products sometime at the beginning of 2021 when Samsung will likely utilize new SoCs in their smartphones. In previous leaks, we have found that the GPU inside this processor is reportedly beating the competition form Qualcomm, where the AMD GPU was compared to Adreno 650. However, today we have obtained more information about the new SoC which is reportedly called "Ryzen C7" smartphone SoC. A new submission to a mobile phone leaks website called Slash Leaks has revealed a lot of new details to us.

The SoC looks like a beast. Manufactured on TSMC 5 nm process, it features two Gaugin Pro cores based on recently announced Arm Cortex-X1, two Gaugin cores based on Arm Cortex-A78, and four cores based on Arm Cortex-A55. This configuration represents a standard big.LITTLE CPU typical for smartphones. Two of the Cortex-X1 cores run at 3 GHz, two of Cortex-A78 run at 2.6 GHz, while four little cores are clocked at 2 GHz frequency. The GPU inside this piece of silicon is what is amazing. It features four cores of custom RDNA 2 based designs that are clocked at 700 MHz. These are reported to beat the Adreno 650 by 45% in performance measurements.

TSMC is working hard to bring the best silicon out there, with the company supplying many of the companies like NVIDIA, AMD, Huawei, and Apple - all customers who demand the latest and greatest when it comes to the silicon technology. According to sources close to DigiTimes, TSMC is expected to kick-off volume production of its next-generation 5 nm+ manufacturing node, which is an enhancement of the 5 nm node, as soon as Q4 of this year hits.

Update May 29th: The DigiTimes report indicates that TSMC is preparing the 5 nm+ node for AMD Ryzen 4000 "Vermeer" series of CPUs. Originally planned for using the 7 nm+ node, the CPUs are supposedly ported to a smaller node, providing better transistor performance and lower power consumption. The Ryzen 4000 series of desktop processors were planned for launching later this year, however, being that the new information provided by DigiTimes suggests 5 nm+ node could be used, we can expect to see Zen 3 based processors sometime in early 2021.

Earlier this week, we brought you a report about codenames of AMD processors that won't launch before 2022. It referenced "Raphael" being distant 5 nm "Zen 4" based successor to today's "Matisse." At the time, the codename for the 2021 release of AMD's mainstream desktop processor wasn't known. We're now getting a pointer as to what it is - "Warhol."

Named after American artist and filmmaker Andy Warhol, this processor combines CPU chiplets based on the "Zen 3" with a cIOD that retains PCI-Express gen 4.0, just like "Vermeer," but still qualifies as a new generation (and not a refresh). What's more, "Warhol" apparently sticks to a 7 nm-class silicon fabrication process. This means that "Warhol" could see AMD innovate on other fronts, such as leveraging an even more advanced version of TSMC's 7 nm node (such as N7+), to increase core counts over the chiplet that makes it to "Vermeer, "Genesis Peak," and "Milan."

Several future AMD processor codenames across various computing segments surfaced courtesy of an Expreview leak that's largely aligned with information from Komachi Ensaka. It does not account for "Matisse Refresh" that's allegedly coming out in June-July as three gaming-focused Ryzen socket AM4 desktop processors; but roadmap from 2H-2020 going up to 2022 sees many codenames surface. To begin with, the second half of 2020 promises to be as action packed as last year's 7/7 mega launch. Over in the graphics business, the company is expected to debut its DirectX 12 Ultimate-compliant RDNA2 client graphics, and its first CDNA architecture-based compute accelerators. Much of the processor launch cycle is based around the new "Zen 3" microarchitecture.

The server platform debuting in the second half of 2020 is codenamed "Genesis SP3." This will be the final processor architecture for the SP3-class enterprise sockets, as it has DDR4 and PCI-Express gen 4.0 I/O. The EPYC server processor is codenamed "Milan," and combines "Zen 3" chiplets along with an sIOD. EPYC Embedded (FP6 package) processors are codenamed "Grey Hawk."

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today announced plans to boost its foundry capacity at the company's new production line in Pyeongtaek, Korea, to meet growing global demand for cutting-edge extreme ultraviolet (EUV) solutions.

The new foundry line, which will focus on EUV-based 5 nanometer (nm) and below process technology, has just commenced construction this month and is expected to be in full operation in the second half of 2021. It will play a pivotal role as Samsung aims to expand the use of state-of-the-art process technologies across a myriad of current and next generation applications, including 5G, high-performance computing (HPC) and artificial intelligence (AI).

It has become a matter of national strategy (or pride) to get TSMC to build a cutting-edge silicon fabrication facility on U.S. soil. Hot on the heals of a report in which TSMC denied it has any plans to build a fab in the U.S., we're learning from a Wall Street Journal that the world's largest independent semiconductor manufacturing company, will build a facility in the U.S. after all. Apparently TSMC will build a silicon fabrication facility in the state of Arizona. The fab will manufacture 5 nm-class chips, to begin with.

TSMC got around to drawing up plans to build a stateside facility after the "involvement" of the State- and Commerce Departments of the U.S. Government. The two are involved not just in coaxing TSMC, but also in the specifics of the planning to get them to the Grand Canyon state. The Donald Trump administration made significant national policy changes with manufacturing, in the wake of the COVID-19 pandemic causing significant wait times in getting silicon products from Asia to the US.Update 01:25 UTC: TSMC made its U.S. fab plans official with an announcement. Press release and additional commentary below.

A DigiTimes premium report, interpreted by Chiakokhua, aka Retired Engineer, chronicling NVIDIA's move to contract TSMC for 7 nm and 5 nm EUV nodes for GPU manufacturing, made a startling revelation about NVIDIA's recent foundry diversification moves. Back in July 2019, a leading Korean publication confirmed NVIDIA's decision to contract Samsung for its next-generation GPU manufacturing. This was a week before AMD announced its first new-generation 7 nm products built for the TSMC N7 node, "Navi" and "Zen 2." The DigiTimes report reveals that NVIDIA underestimated the efficiency gains AMD would yield from TSMC N7.

With NVIDIA's bonhomie with Samsung underway, and Apple transitioning to TSMC N5, AMD moved in to quickly grab 7 nm-class foundry allocation and gained prominence with the Taiwanese foundry. The report also calls out a possible strategic error on NVIDIA's part. Upon realizing the efficiency gains AMD managed, NVIDIA decided to bet on TSMC again (apparently without withdrawing from its partnership with Samsung), only to find that AMD had secured a big chunk of its nodal allocation needed to support its growth in the x86 processor and discrete GPU markets. NVIDIA has hence decided to leapfrog AMD by adapting its next-generation graphics architectures to TSMC's EUV nodes, namely the N7+ and N5. The report also speaks of NVIDIA using its Samsung foundry allocation as a bargaining chip in price negotiations with TSMC, but with limited success as TSMC established its 7 nm-class industry leadership. As it stands now, NVIDIA may manufacture its 7 nm-class and 5 nm-class GPUs on both TSMC and Samsung.

Samsung in its Q1-2020 financials release disclosed that the company will commence mass production of chips on its cutting-edge 5 nanometer EUV silicon fabrication process within Q2-2020 (that's before July 2020). This is big, as it lends credence to rumors of NVIDIA secretly developing 5 nm GPUs. Suddenly, it's possible that "Ampere," if not "Hopper," is 5 nm EUV-based, as NVIDIA has chosen Samsung to be its foundry partner for next-generation GPUs.

"In the second quarter, the Company aims to expand EUV leadership, beginning with the start of mass production of 5 nm products, while closely monitoring the uncertain market situation caused by COVID-19," the company states in the release. Samsung also announced that following commencement of mass production on 5 nm, further development of GAAFET (gate all-around FET) 3 nanometer silicon fabrication process will get underway. The company appears to be erring on the side of caution with its forward-looking statements, though. Much of what Samsung does will be dictated by the impact of COVID-19 on the supply chain and market.

AMD is expected to support the next-generation DDR5 memory standard by 2022, according to a MyDrivers report citing industry sources. We are close to a change in memory standards, with the 5-year old DDR4 memory standard beginning a gradual phase out over the next 3 years. Leading DRAM manufacturers such as SK Hynix have already hinted mass-production of the next-generation DDR5 memory to commence within 2020. Much like with DDR4, Intel could be the first to market with processors that support it, likely with its "Sapphire Rapids" Xeon processors. AMD, on the other hand, could debut support for the standard only with its "Zen 4" microarchitecture slated for 2021 technology announcements, with 2022 availability.

AMD "Zen 4" will see a transition to a new silicon fabrication process, likely TSMC 5 nm-class. It will be an inflection point for the company from an I/O standpoint, as it sees the introduction of DDR5 memory support across enterprise and desktop platforms, LPDDR5 on the mobile platform, and PCI-Express gen 5.0 across the board. Besides a generational bandwidth doubling, PCIe gen 5.0 is expected to introduce several industry-standard features that help with hyper-scalability in the enterprise segment, benefiting compute clusters with multiple scalar processors, such as AMD's CDNA2. Intel introduced many of these features with its proprietary CXL interconnect. AMD's upcoming "Zen 3" microarchitecture, scheduled for within 2020 with market presence in 2021, is expected to stick with DDR4, LPDDR4x, and PCI-Express gen 4.0 standards. DDR5 will enable data-rates ranging between 3200 to 8400 MHz, densities such as single-rank 32 GB UDIMMs, and a few new physical-layer features such as same-bank refresh.

A report via DigiTimes places TSMC as having announced to its investors that exploratory studies and R&D for the development of the 2 nm process node have commenced. As today's leading semiconductor fabrication company, TSMC doesn't seem to be one resting on its laurels. Their 7 nm process and derivatives have already achieved a 30% weight on the company's semiconductor orders, and their 5 nm node (which will include EUV litography) is set to hit HVM (High Volume Manufacturing) in Q2 of this year. Apart from that, not much more is known on 2 nm.

After 5 nm, which is expected to boats of an 84-87% transistor density gain over the current 7nm node, the plans are to go 3nm, with TSMC expecting that node to hit mass production come 2022. Interestingly, TSMC is planning to still use FinFET technology for its 3 nm manufacturing node, though in a new GAAFET (gate-all-around field-effect transistor) technology. TSMC's plans to deploy FinFET in under 5nm manufacturing is something that many industry analysts and specialist thought extremely difficult to achieve, with expectations for these sub-5nm nodes to require more exotic materials and transistor designs than TSMC's apparent plans

According to the report of DigiTimes, which talked about TSMC's 5 nm silicon manufacturing node, they have reported that NVIDIA is also going to be a customer for it and they could use it in the near future. And that is very interesting information, knowing that these chips will not go in the next generation of GPUs. Why is that? Because we know that NVIDIA will utilize both TSMC and Samsung for their 7 nm manufacturing nodes for its next-generation Ampere GPUs that will end up in designs like GeForce RTX 3070 and RTX 3080 graphics cards. These designs are not what NVIDIA needs 5 nm for.

Being that NVIDIA already has a product in its pipeline that will satisfy the demand for the high-performance graphics market, maybe they are planning something that will end up being a surprise to everyone. No one knows what it is, however, the speculation (which you should take with a huge grain of salt) would be that NVIDIA is updating its Tegra SoC with the latest node. That Tegra SoC could be used in a range of mobile devices, like the Nintendo Switch, so could NVIDIA be preparing a new chip for Nintendo Switch 2?

Imagine being able to shrink a Pentium 4 processor die to the size of a pin-head (if you can figure out how to place 478 bumps on it). TSMC revealed that its future 3 nanometer silicon fabrication node has a development target of 250 million transistors per mm². Called N3, the next-generation silicon fabrication node succeeds TSMC's N5 family of 5 nm-class nodes (that's N5 and any possible refinements).

TSMC CEO CC Wei confirmed that development of the 3 nm node is on-track, with risk production scheduled for 2021 and volume production commencing in the second half of 2022. Perhaps the most startling revelation is that TSMC has decided to stick with FinFETs for N3 owing to the maturity of the technology. Experts are of the opinion that sub-5 nm nodes will require major innovations with materials and structures. TSMC claims that N3 will provide a 10-15% speed improvement at iso-power or 25-30% power reduction at iso-speed, compared to N5.

With Mainland Chinese tech giant Huawei being effectively cut off from contracting Taiwanese TSMC to manufacture its next-generation HiSilicon 5G mobile SoCs, and NVIDIA switching to Samsung for its next-generation GPUs, TSMC is looking to hold on to large high-volume customers besides Apple and Qualcomm, so as to not let them dictate pricing. AMD is at the receiving end of the newfound affection, with the semiconductor firm reportedly developing a new refinement of its 5 nm node specially for AMD, possibly to make Sunnyvale lock in on TSMC for its future chip architectures. A ChainNews report decoded by @chiakokhua sheds light on this development.

AMD is developing its "Zen 4" CPU microarchitecture for a 5 nm-class silicon fabrication node, although the company doesn't appear to have zeroed in on a node for its RDNA3 graphics architecture and CDNA2 scalar compute architecture. In its recent public reveal of the two, AMD chose not to specify the foundry node for the two, which come out roughly around the same time as "Zen 4." It wouldn't be far fetched to predict that AMD and TSMC were waiting on certainty for the new 5 nm-class node's development. There are no technical details of this new node. AMD's demand for TSMC is expected to be at least 20,000 12-inch wafers per month.

TSMC will be doing good on their previous expectations for a H2 2020 ramp-up for high volume production (HVM) on their 5 nm manufacturing process. The new 5 nm fabrication process is an Extreme Ultraviolet lithography (EUV) one, with up to 14 layers being etchable onto the silicon wafers, as opposed to five and six, respectively, for TSMC's N7+ and N6 processes.

Volume production will start with Apple's A14 SoC, meant to be driving next-generation iPhones that should hit shelves by September this year (should the COVID-19 pandemic let it be so). Apple is using two thirds of TSMC's capacity for 5 nm as is with this SoC; it's currently unclear which client (or clients) are getting the leftover one third capacity. TSMC announced back in December that they were seeing yields upwards of 80% in 5 nm EUV fabrication, so now it's "just" a matter of monetizing the process until their 3 nm iteration comes online, expectedly, in 2022.

With its 7 nm RDNA architecture that debuted in July 2019, AMD achieved a nearly 50% gain in performance/Watt over the previous "Vega" architecture. At its 2020 Financial Analyst Day event, AMD made a big disclosure: that its upcoming RDNA2 architecture will offer a similar 50% performance/Watt jump over RDNA. The new RDNA2 graphics architecture is expected to leverage 7 nm+ (7 nm EUV), which offers up to 18% transistor-density increase over 7 nm DUV, among other process-level improvements. AMD could tap into this to increase price-performance by serving up more compute units at existing price-points, running at higher clock speeds.

AMD has two key design goals with RDNA2 that helps it close the feature-set gap with NVIDIA: real-time ray-tracing, and variable-rate shading, both of which have been standardized by Microsoft under DirectX 12 DXR and VRS APIs. AMD announced that RDNA2 will feature dedicated ray-tracing hardware on die. On the software side, the hardware will leverage industry-standard DXR 1.1 API. The company is supplying RDNA2 to next-generation game console manufacturers such as Sony and Microsoft, so it's highly likely that AMD's approach to standardized ray-tracing will have more takers than NVIDIA's RTX ecosystem that tops up DXR feature-sets with its own RTX feature-set.

AMD at its 2020 Financial Analyst Day event unveiled its upcoming CDNA GPU-based compute accelerator architecture. CDNA will complement the company's graphics-oriented RDNA architecture. While RDNA powers the company's Radeon Pro and Radeon RX client- and enterprise graphics products, CDNA will power compute accelerators such as Radeon Instinct, etc. AMD is having to fork its graphics IP to RDNA and CDNA due to what it described as market-based product differentiation.

Data centers and HPCs using Radeon Instinct accelerators have no use for the GPU's actual graphics rendering capabilities. And so, at a silicon level, AMD is removing the raster graphics hardware, the display and multimedia engines, and other associated components that otherwise take up significant amounts of die area. In their place, AMD is adding fixed-function tensor compute hardware, similar to the tensor cores on certain NVIDIA GPUs.

TSMC today announced it has collaborated with Broadcom on enhancing the Chip-on-Wafer-on-Substrate (CoWoS ) platform to support the industry's first and largest 2X reticle size interposer. With an area of approximately 1,700mm2, this next generation CoWoS interposer technology significantly boosts computing power for advanced HPC systems by supporting more SoCs as well as being ready to support TSMC's next-generation five-nanometer (N5) process technology.

This new generation CoWoS technology can accommodate multiple logic system-on-chip (SoC) dies, and up to 6 cubes of high-bandwidth memory (HBM), offering as much as 96 GB of memory. It also provides bandwidth of up to 2.7 terabytes per second, 2.7 times faster than TSMC's previously offered CoWoS solution in 2016. With higher memory capacity and bandwidth, this CoWoS solution is well-suited for memory-intensive workloads such as deep learning, as well as workloads for 5G networking, power-efficient datacenters, and more. In addition to offering additional area to increase compute, I/O, and HBM integration, this enhanced CoWoS technology provides greater design flexibility and yield for complex ASIC designs in advanced process nodes.