Intel has today released the 43rd edition of its x86/x64 ISA developer manual designed to help developers see what's new in x86 world and make software optimizations for Intel's platform. In the latest edition of the manual, Intel has revealed the details of its low-power x86 "Tremont" architecture designed for 10 nm efficient, low-power computing. Announced last year in October, Intel promised to deliver a big IPC increase compared to the previous generation low-power CPU microarchitecture like the Goldmont Plus family. To achieve extra performance, Intel has implemented a lot of new solutions.

For starters, Tremont boasts better branch prediction unit, with increased capacity for instruction queue and better path-based conditional and indirect prediction. The front-end fetch and decode pipeline have been updated as well. Now the design is a 6-wide Out of Order Execution (OoOE) pipeline which can process 6 instructions per cycle. The Data cache is now upgraded to 32 KB. The load and store execution pipelines are now doubled and they are capable of two loads and two stores, or one load and one store, depending on the application. Tremont also updates on one important point and that is a dedicated store data port for integer and vector integer/floating-point data. Another big improvement is happening in the cryptography department. Tremont now features Galois-field instructions labeled as the GFNI family of instructions. There are two AES units for faster AES encryption and decryption. The already implemented SHA-NI cryptography standard was enhanced and it now is much faster as well. For mode in-depth report please check out Intel's x86/x64 manual.

MSI IPC launches the IoT edge computers, MS-9A77 & MS-9A97 positioned in high-performance products with high efficiency and low energy consumption. This ultra-compact and fanless embedded computer with 3 sides I/O interface, slim type, anti-vibration and shockproof designed to compliance IEC 61373. The DIN-rail mounting form factor is suitable to be used in control cabinet for industrial automation application.

Moreover, it also supports MSI IPC's exclusive HIDAC Industrial IoT software for smart device monitoring and management. This slim industrial computer is with DIN-rail installation and can be mounted using VESA or wall mount as an option.

PTT leaked some juicy details of the upcoming Intel "Rocket Lake" and "Alder Lake" processor generations. "Rocket Lake" will power Intel's 11th generation Core processor series in the LGA1200 package, and are rumored to be a "back port" of Intel's advanced "Willow Cove" CPU cores to a 14 nm-class silicon fabrication node, with core-counts ranging up to 8. The idea for Intel is to sell high IPC, high clock-speed desktop processors for gaming.

According to the PTT report, there will be three kinds of SKUs for "Rocket Lake" based on TDP: 8-core parts with 95 W TDP rating; and 8-core, 6-core, and 4-core parts in 80 W TDP and 65 W TDP variants. For the 95 W (PL1) parts, the power-levels PL2, and PL4 are reportedly set at 173 W and 251 W, respectively, and a 56-second Tau (a timing variable that dictates how long a processor can stick around at an elevated power-state before retreating to PL1, which is interchangeable with the TDP value on the box). The 80 W TDP parts feature 146 W PL2, 191 W PL3, and 251 W PL4, but a lower Tau value of 28 seconds. For the 65 W parts, the PL2 is 128 W, PL3 is 177 W, and PL4 251 W, and the Tau value 28 seconds.

AMD has reportedly updated its Ryzen 3 1200 CPU with Zen+ architecture and is now offering it to consumers. Featuring a configuration of 4 cores with 4 threads, this CPU can operate anywhere from 3.1 GHz (base) to 3.4 GHz in boost frequency. Having originally launched in July of 2017, just under three years ago, AMD decided to refresh this CPU with Zen+ architecture, which brought improvements like a tiny IPC increase, better turbo boost speeds, faster caches and better memory controller for better support of faster DDR4 modules.

The new "Zen+" revision has the same specifications as the older model, however, the only difference is the newer 12 nm manufacturing process and some of the architecture changes of Zen+. The rest of the specifications like clock speeds are the same. The CPU is listed by a German supplier for €54.73 or about $60. This revision carries a different part number, under the code "YD1200BBM4KAFBOX", where the older 14 nm model was "YD1200BBM4KAEBOX".

AMD's Zen 3 architecture will power the next generation Ryzen 4000 desktop chips and the 3rd Gen EPYC lineup which are both expected to launch later this year. Adored TV has received some leaked information detailing the technical specifications of the Zen 3 architecture. The majority of the leaked information confirmed existing rumors such as the 8 core CCX, higher clocks and lower power draw.

However the leak suggests IPC improvements will be less than the expected 20% hinted at by AMD and may end up being closer to 10 - 15%. The leak also claims that L3 cache will remain at 32 MB however it will no longer be split due to the single CCX. While this may be disappointing for some, remember to take the claims with a grain of salt as with any rumor.

AMD at its 2020 Financial Analyst Day event unveiled its upcoming CDNA GPU-based compute accelerator architecture. CDNA will complement the company's graphics-oriented RDNA architecture. While RDNA powers the company's Radeon Pro and Radeon RX client- and enterprise graphics products, CDNA will power compute accelerators such as Radeon Instinct, etc. AMD is having to fork its graphics IP to RDNA and CDNA due to what it described as market-based product differentiation.

Data centers and HPCs using Radeon Instinct accelerators have no use for the GPU's actual graphics rendering capabilities. And so, at a silicon level, AMD is removing the raster graphics hardware, the display and multimedia engines, and other associated components that otherwise take up significant amounts of die area. In their place, AMD is adding fixed-function tensor compute hardware, similar to the tensor cores on certain NVIDIA GPUs.

Alleged pictures of the upcoming Intel Core i9-10900K and i7-10700K processors made it to Chinese social media. The blurry-cam pictures of the chips' topside don't reveal much other than the "Intel Confidential" markings, denoting that these chips are engineering samples. The reverse side confirm that these are chips are built in the new LGA1200 package. You can also spot electrical ancillaries laid out unlike any previous-gen Intel package, and different socket key notches.

In the run up to the rumored April 2020 launch we could learn more about these chips. Based on the 14 nm "Comet Lake" silicon, Intel's 10th generation Core desktop processors in the LGA1200 package increase logical processor counts across the board, and increase clock speeds. The i9-10900K is a 10-core/20-thread processor with 20 MB of shared L3 cache, and up to 5.10 GHz boost frequency, with 4.80 GHz all-core boost. The i7-10700K, on the other hand, is an 8-core/16-thread chip with 16 MB L3 cache, and clock speeds of 5.00 GHz boost and 4.50 GHz all-core Turbo. The Core i5 series also gets a shot in the arm, being configured as 6-core/12-thread, with 12 MB of L3 cache. The per-core performance (IPC) is expected to be the same as 6th generation "Skylake."

Since its switch to the x86 machine architecture from PowerPC in the mid-2000s, Apple has been consistent with Intel as its sole supplier of CPUs for its Macbooks, iMac desktops, and Mac Pro workstations. The company's relationship with rival AMD has been limited to sourcing discrete GPUs. If pieces of code from a MacOS beta is anything to go buy, Apple could bite the AMD bullet very soon. References to several AMD processors were found in MacOS 10.15.4 Beta 1. These include the company's "Picasso," "Renoir," and "Van Gogh" APUs.

It's very likely that with increasing CPU IPC and energy-efficiency, Apple is finally seeing the value in single-chip solutions from AMD that have a good enough combination of CPU and iGPUs. The 7 nm "Renoir" silicon in particular could change the mobile and desktop computing segments, thanks to its 8-core "Zen 2" CPU, and a "Vega" based iGPU that's highly capable in non-gaming and light-gaming tasks. AMD's proprietary SmartShift feature could also be leveraged, which dynamically switches between the iGPU and an AMD discrete GPU.

At a media event on Wednesday, Intel invited us to check out their first working modern discrete graphics card, the Xe DG1 Software Development Vehicle (developer-edition). Leading the event was our host Ari Rauch, Intel Vice President and General Manager for Graphics Technology Engineering and dGPU Business. Much like gruff developer-editions of game consoles released to developers several quarters ahead of market launch, the DG1-SDV allows software developers to discover and learn the Xe graphics architecture, and develop optimization processes for their current and future software within their organizations. We walked into the event expecting to see a big ugly PCB with a bare fan-heatsink and a contraption that sort-of looks like a graphics card; but were pleasantly surprised with what we saw: a rather professional product design.

What we didn't get at the event, through, was a juicy technical breakdown of the Xe graphics architecture, and its various components that add up to the GPU. We still left pleasantly surprised for what we were shown: it works! The DG1-SDV is able to play games at 1080p, even if they are technically lightweight titles like "Warframe," and aren't maxing out settings. The SDV is a 15.2 cm-long graphics card that relies on the PCI-Express slot for power entirely (and hence pulling less than 75 W).

A prominent Taiwanese newspaper reported that AMD will formally unveil its next-generation "Zen 3" CPU microarchitecture at the 2020 International CES. Company CEO Dr Lisa Su will head an address revealing three key client-segment products under the new 4th generation Ryzen processor family, and the company's 3rd generation EPYC enterprise processor family based on the "Milan" MCM that succeeds "Rome." AMD is keen on developing an HEDT version of "Milan" for the 4th generation Ryzen Threadripper family, codenamed "Genesis Peak."

The bulk of the client-segment will be addressed by two distinct developments, "Vermeer" and "Renoir." The "Vermeer" processor is a client-desktop MCM that succeeds "Matisse," and will implement "Zen 3" chiplets. "Renoir," on the other hand, is expected to be a monolithic APU that combines "Zen 2" CPU cores with an iGPU based on the "Vega" graphics architecture, with updated display- and multimedia-engines from "Navi." The common thread between "Milan," "Genesis Peak," and "Vermeer" is the "Zen 3" chiplet, which AMD will build on the new 7 nm EUV silicon fabrication process at TSMC. AMD stated that "Zen 3" will have IPC increases in line with a new microarchitecture.

Intel's latest talent acquisition from rival AMD, as it builds a GPU product lineup, is Masooma Bhaiwala. "After 15+ amazing years at AMD, I have decided to take on a different opportunity... It was a truly fun ride, with an incredible team, during which we built some truly cool chips," she wrote in a LinkedIn post. According to her profile, Bhaiwala takes the role of Vice President, discrete GPU SoCs, and works under Intel's Graphics and Throughput Computing Hardware Engineering group headed by Raja Koduri.

Koduri's team has been a glassdoor for former AMD executives and tech-leads. While it has hired engineering talent such as Balaji Kanigicherla, Kalyan Thumaty and Joseph Facca; it has simultaneously lost client-graphics marketing talent, with the likes of Chris Hook, Heather Lennon, and Jon Carvill waltzing out of the company in less than a year of their association. Besides Koduri's Intel's most priced tech talent acquisition is Jim Keller, who is working on a future high-IPC CPU core design for the company. While working for AMD, Keller's "Zen" microarchitecture coupled with CEO Lisa Su's leadership have scripted one of the biggest turnarounds in Silicon Valley.

At its recent SC19 talk, AMD touched upon its upcoming "Zen 3" CPU microarchitecture. Designed for the 7 nm EUV silicon fabrication process that significantly increases transistor densities, "Zen 3" could post performance gains "right in line with what you would expect from an entirely new architecture," states AMD, referring to the roughly 15 percent IPC gains that were expected of "Zen 2" prior to its launch. "Zen 2" IPC ended up slightly over 15 percent higher than that of the original "Zen" microarchitecture. AMD's SC19 comments need not be a guidance on the IPC itself, but rather performance gains of end-products versus their predecessors.

The 7 nm EUV process, with its 20 percent transistor-density increase could give AMD designers significant headroom to increase clock speeds to meet the company's generational performance improvement targets. Another direction in which "Zen 3" could go is utilizing the additional transistor density to bolster its core components to support demanding instruction-sets such as AVX-512. The company's microarchitecture is also missing something analogous to Intel's DLBoost, an instruction-set that leverages fixed-function hardware to accelerate AI-DNN building and training. Even VIA announced an x86 microarchitecture with AI hardware and AVX-512 support. In either case, the design of "Zen 3" is complete. We'll have to wait until 2020 to find out how fast "Zen 3" is, and the route taken to get there.

Intel CFO George Davis in an interview with Barron's commented on the company's financial health, and some of the reasons behind its rather conservative gross margin guidance looking forward to at least 2023. Intel's current product stack is moving on to the company's 10 nm silicon fabrication process in a phased manner. The company is allocating 10 nm to mobile processors and enterprise processors, while brazening it out with 14 nm on the client-desktop and HEDT platforms until they can build 10 nm desktop parts. AMD has deployed its high-IPC "Zen 2" microarchitecture on TSMC's 7 nm DUV process, with plans to go EUV in the coming months.

"We're still keenly focused on gross margin. Everything from capital efficiency to the way we're designing our products. What we've said though, the delay in 10 nanometer means that we're going to be a little bit disadvantaged on unit cost for a period of time. We actually gave guidance for gross margin out in 2021 to help people understand. 2023 is the period that we were ultimately guiding [when] we're going to see very strong revenue growth and margin expansion. We've got to get through this period where we have the 10 nanometer being a little bit late [as] we're not optimized on a node that we're on. But [by] then we're moving to a two to two and a half year cadence on the next nodes. So we're pulling in the spending on 7 nanometer, which will start up in the second half of 2021 because we think it's the right thing to do competitively," he said.

AMD's upcoming Ryzen 9 3950X socket AM4 processor beats Intel's flagship 18-core processor, the Core i9-10980XE, by a staggering 24 percent at 3DMark Physics, according to a PC Perspective report citing TUM_APISAK. The 3950X is a 16-core/32-thread processor that's drop-in compatible with any motherboard that can run the Ryzen 9 3900X. The i9-10980XE is an 18-core/36-thread HEDT chip that enjoys double the memory bus width as the AMD chip, and is based on Intel's "Cascade Lake-X" silicon. The AMD processor isn't at a tangible clock-speed advantage. The 3950X has a maximum boost frequency of 4.70 GHz, while the i9-10980XE isn't much behind, at 4.60 GHz, but things differ with all-core boost.

When paired with 16 GB of dual-channel DDR4-3200 memory, the Ryzen 9 3950X powered machine scores 32,082 points in the CPU-intensive physics tests of 3DMark. In comparison, the i9-10980XE, paired with 32 GB of quad-channel DDR4-2667 memory, scores just 25,838 points as mentioned by PC Perspective. Graphics card is irrelevant to this test. It's pertinent to note here that the 3DMark physics test scales across practically any number of CPU cores/threads, and the AMD processor could be benefiting from a higher all-core boost frequency than the Intel chip. Although AMD doesn't mention a number in its specifications, the 3950X is expected to have an all-core boost frequency that's north of 4.00 GHz, as its 12-core sibling, the 3900X, already offers 4.20 GHz all-core. In contrast, the i9-10980XE has an all-core boost frequency of 3.80 GHz. This difference in boost frequency, apparently, even negates the additional 2 cores and 4 threads that the Intel chip enjoys, in what is yet another example of AMD having caught up with Intel in the IPC game.

Intel at the Intel Developer Conference 'IDC' 2019 in Tokyo revealed their performance projections for mobility Xe GPUs, which will supersede their current consumer-bound UHD620 graphics under the Gen 11 architecture. The company is being vocal in that they can achieve an up to 2x performance uplift over their previous generation - but that will likely only take place in specific scenarios, and not as a rule of thumb. Just looking at Intel's own performance comparison graphics goes to show that we're mostly looking at between 50% and 70% performance improvements in popular eSports titles, which are, really, representative of most of the gaming market nowadays.

The objective is to reach above 60 FPS in the most popular eSports titles, something that Gen 11 GPUs didn't manage with their overall IPC and dedicated die-area. We've known for some time that Intel's Xe (as in, exponential) architecture will feature hardware-based raytracing, and the architecture is being developed for scalability that goes all the way from iGPUs to HPC platforms.

There is no correlation between CPU frequency boosting behavior and system stability. Intel today launched its "10th generation" Core X HEDT processors, with core-counts ranging between 10 to 18, priced between $590 and $978. Based on the 14 nm "Cascade Lake-X" silicon, these chips have the same exact IPC as "Skylake" circa 2015, but offer nearly double the number of cores to the Dollar compared to the 9th generation Core X series; and add a couple of useful instruction sets such as DLBoost, which accelerates DNN training/building; a few more AVX-512 instructions, and an updated Turbo Boost Max 3.0 algorithm. The chips offer clock-speed bumps over the previous generation.

Intel's main trade-call for these processors? Taking another stab at AMD for falling short on boost frequency in the hands of consumers. "The chip that hits frequency benchmarks as promised, our new #CoreX -series processor, provides a stable, high-performance platform for visual creators everywhere," reads the Intel tweet, as if to suggest that reaching the "promised" clock speed results in stability. AMD was confronted with alarming statistics of consumers whose 3rd generation Ryzen processors wouldn't reach their advertised boost frequencies. The company released an updated AGESA microcode that fixed this.

Intel is preparing to increase core-counts across the board with its upcoming Core X "Cascade Lake-X" HEDT processor family, launching next month. The first indication of this comes from an Intel slide that claims a 1.74 to 2.09x increase in performance-per-Dollar over "Skylake-X." The "Cascade Lake" microarchitecture already made its debut in the enterprise market as Intel's 2nd generation Xeon Scalable processors, and its IPC is similar clock-to-clock, to its predecessor (Skylake).

If Intel is claiming such performance-per-Dollar increases, it only points to a significant increase in core counts to the Dollar (think 16-core at $999, 28-core at $1999, etc.). Adding value to these chips are certain new AI accelerating instruction sets, such as DLBoost, support for Optane DC Persistent Memory, increased memory clock-speeds, and higher CPU clocks across the board compared to the Core X 9000-series. The Core X "Cascade Lake-X" processor family debuts this October.

AMD in its 2nd generation EPYC processor launch event announced that it has completed the design phase of its next-generation "Zen 3" CPU microarchitecture, and is currently working on its successor, the "Zen 4." AMD debuted its "Zen 2" microarchitecture with the client-segment 3rd generation Ryzen desktop processor family, it made its enterprise debut with the 2nd generation EPYC. This is the first x86 CPU microarchitecture designed for the 7 nanometer silicon fabrication process, and is being built on a 7 nm DUV (deep ultraviolet) node at TSMC. It brings about double-digit percentage IPC improvements over "Zen+."

The "Zen 3" microarchitecture is designed for the next big process technology change within 7 nm, EUV (extreme ultraviolet), which allows significant increases in transistor densities, and could facilitate big improvements in energy-efficiency that could be leveraged to increase clock-speeds and performance. It could also feature new ISA instruction-sets. With "Zen 3" passing design phase, AMD will work on prototyping and testing it. The first "Zen 3" products could debut in 2020. "Zen 4" is being designed for a different era.

At a launch event today, AMD was joined by an expansive ecosystem of datacenter partners and customers to introduce the 2nd Generation AMD EPYC family of processors that deliver performance leadership across a broad number of enterprise, cloud and high-performance computing (HPC) workloads. 2nd Gen AMD EPYC processors feature up to 64 "Zen 2" cores in leading-edge 7 nm process technology to deliver record-setting performance while helping reduce total cost of ownership (TCO) by up to 50% across numerous workloads. At the event, Google and Twitter announced new 2nd Gen AMD EPYC processor deployments and HPE and Lenovo announced immediate availability of new platforms.

"Today, we set a new standard for the modern datacenter with the launch of our 2nd Gen AMD EPYC processors that deliver record-setting performance and significantly lower total cost of ownership across a broad set of workloads," said Dr. Lisa Su, president and CEO, AMD. "Adoption of our new leadership server processors is accelerating with multiple new enterprise, cloud and HPC customers choosing EPYC processors to meet their most demanding server computing needs."

AMD (NASDAQ:AMD) today announced revenue for the second quarter of 2019 of $1.53 billion, operating income of $59 million, net income of $35 million and diluted earnings per share of $0.03. On a non-GAAP basis, operating income was $111 million, net income was $92 million and diluted earnings per share was $0.08.

"I am pleased with our financial performance and execution in the quarter as we ramped production of three leadership 7nm product families," said Dr. Lisa Su, AMD president and CEO. "We have reached a significant inflection point for the company as our new Ryzen, Radeon and EPYC processors form the most competitive product portfolio in our history and are well positioned to drive significant growth in the second half of the year."

During its second quarter earnings call, Intel announced that it has started shipping of 10th generation "Core" CPUs to OEMs. Making use of 10 nm lithography, the 10th generation of "Core" CPUs, codenamed Ice Lake, were qualified by OEMs earlier in 2019 in order to be integrated into future products. Ice Lake is on track for holiday season 2019, meaning that we can expect products on-shelves by the end of this year. That is exciting news as the 10th generation of Core CPUs is bringing some exciting micro-architectural improvements along with the long awaited and delayed Intel's 10nm manufacturing process node.

The new CPUs are supposed to get around 18% IPC improvement on average when looking at direct comparison to previous generation of Intel CPUs, while being clocked at same frequency. This time, even regular mobile/desktop parts will get AVX512 support, alongside VNNI and Cryptography ISA extensions that are supposed to bring additional security and performance for the ever increasing number of tasks, especially new ones like Neural Network processing. Core configurations will be ranging from dual core i3 to quad core i7, where we will see total of 11 models available.

Market availability of the 16-core Ryzen 9 3950X may be far away, given its September 2019 launch, but engineering samples (ESes) of the chip seem to be already in circulation. "uzzi38" on Twitter posted this spy-shot of a 3950X ES making short work of Cinebench R15. CPU-Z recognizes the chip by its codename "Matisse," and puts out the correct CPU core and thread count, but doesn't give a name-string. It also recognizes the MSI MEG X570 GODLIKE motherboard this test is run on.

The purported Ryzen 9 3950X ES, overclocked to 5.42 GHz, scores a gargantuan 5,501 points in the multi-threaded benchmark. To put this number into perspective, at stock frequencies, a Ryzen Threadripper 2950X (same core-count, double the memory bus width), scores 3,645 points. The 3950X benefits from not just its massive overclock that's over 1 GHz higher than the stock TR-2950X, but also higher IPC, and a more consolidated memory interface. This feat goes to show that AMD's upcoming Ryzen chips love to overclock, and deliver a significantly higher single-thread performance over the previous generation.

Intel is embattled in the client-segment desktop processor business, with AMD's imminent launch of its 3rd generation Ryzen desktop processors. Intel's 9th generation Core processors may lose their competitiveness to AMD's offerings, and are expected to get relieved by the company's "Ice Lake" desktop processors only in 2020. Until then, Intel will market its processors through price-cuts, promotions, bundles, and focusing on their gaming prowess. The company will refresh its HEDT (high-end desktop) processor lineup some time in Q3-2019. According to Taiwan-based industry observer DigiTimes citing sources in the motherboard industry, Intel's immediate response to 3rd generation Ryzen will be a series of price-cuts to products in its client-segment DIY retail channel.

According to these sources, prices of 9th generation Core processors could be cut by a minimum of 10 percent, and a maximum of 15 percent, varying by SKUs. This could see prices of popular gaming/enthusiast SKUs such as the Core i9-9900K, the i7-9700K, and the i5-9600K, drop by anywhere between $25 to $75. AMD is launching the Ryzen 9 3900X to compete with the i9-9900K, the Ryzen 7 3800X to compete with the i7-9700K, and the Ryzen 5 3600X to take on the i5-9600K. The three SKUs, according to AMD's internal testing, match the Intel chips at gaming, and beat them at content-creation tasks. At the heart of 3rd generation Ryzen processors is AMD's new Zen 2 microarchitecture, which brings significant IPC gains. AMD is also increasing core-counts on its mainstream desktop platform with the introduction of the Ryzen 9 family of 12-core and 16-core processors in the AM4 package.

Intel late-May made its first major disclosure of the per-core CPU performance gains achieved with its "Ice Lake" processor that packs "Sunny Cove" CPU cores. Averaged across a spectrum of benchmarks, Intel claims a best-case scenario IPC (instructions per clock) uplift of a massive 40 percent over "Skylake," and a mean uplift of 18 percent. The worst-case scenario sees its performance negligibly below that of "Skylake." Intel's IPC figures are derived entirely across synthetic benchmarks, which include SPEC 2016, SPEC 2017, SYSMark 2014 SE, WebXprt, and CineBench R15. The comparison to "Skylake" is relevant because Intel has been using essentially the same CPU core in the succeeding three generations that include "Kaby Lake" and "Coffee Lake."

A Chinese tech-forum member with access to an "Ice Lake" 6-core/12-thread sample put the chip through the CPU-Z internal benchmark (test module version 17.01). At a clock-speed of 3.60 GHz, the "Ice Lake" chip allegedly achieved a single-core score of 635 points. To put this number into perspective, a Ryzen 7 3800X "Matisse" supposedly needs to run at 4.70 GHz to match this score, and a Core i7-7700K "Kaby Lake" needs to run at 5.20 GHz. Desktop "Ice Lake" processors are unlikely to launch in 2019. The first "Ice Lake" processors are 4-core/8-thread chips designed for ultraportable notebook platforms, which come out in Q4-2019, and desktop "Ice Lake" parts are expected only in 2020.

AMD "Navi 10" is a very different GPU from the "Vega 10," or indeed the "Polaris 10." The GPU sees the introduction of the new RDNA graphics architecture, which is the first big graphics architecture change on an AMD GPU in nearly a decade. AMD had in 2011 released its Graphics CoreNext (GCN) architecture, and successive generations of GPUs since then, brought generational improvements to GCN, all the way up to "Vega." At the heart of RDNA is its brand new Compute Unit (CU), which AMD redesigned to increase IPC, or single-thread performance.

Before diving deeper, it's important to confirm two key specifications of the "Navi 10" GPU. The ROP count of the silicon is 64, double that of the "Polaris 10" silicon, and same as "Vega 10." The silicon has sixteen render-backends (RBs), these are quad-pumped, which work out to an ROP count of 64. AMD also confirmed that the chip has 160 TMUs. These TMUs are redesigned to feature 64-bit bi-linear filtering. The Radeon RX 5700 XT maxes out the silicon, while the RX 5700 disables four RDNA CUs, working out to 144 TMUs. The ROP count on the RX 5700 is unchanged at 64.