Parallels has announced the introduction of x86 emulation support in Parallels Desktop 20.2.0 for Apple Silicon Macs. This new feature enables users to run x86-based virtual machines on their M-series Mac computers, addressing a longstanding limitation since Apple's transition to its custom Arm-based processors. The early technology preview allows users to run Windows 10, Windows 11 (with some restrictions), Windows Server 2019/2022, and various Linux distributions through a proprietary emulation engine. This development particularly benefits developers and users who need to run 32-bit Windows applications or prefer x86-64 Linux virtual machines as an alternative to Apple Rosetta-based solutions.

However, Parallels is transparent about the current limitations of this preview release. Performance is notably slow, with Windows boot times ranging from 2 to 7 minutes, and overall system responsiveness remains low. The emulation only supports 64-bit operating systems, though it can run 32-bit applications. Additionally, USB device support is not available, and users must rely on Apple's hypervisor as the Parallels hypervisor isn't compatible. Despite these constraints, the release is a crucial step forward in bridging the compatibility gap for Apple Silicon Mac users so legacy software can still be used. The feature has been implemented with the option to start virtual machines hidden in the user interface to manage expectations, as it is still imperfect.

Ultra Accelerator Link Consortium (UALink) has announced the expansion of its Board of Directors with the election of Alibaba Cloud Computing Ltd., Apple Inc., and Synopsys Inc. The new Board members will leverage their industry knowledge to advance development and industry adoption of UALink - a high-speed, scale-up interconnect for next-generation AI cluster performance.

"Alibaba Cloud believes that driving AI computing accelerator scale-up interconnection technology by defining core needs and solutions from the perspective of cloud computing and applications has significant value in building the competitiveness of intelligent computing supernodes," said Qiang Liu, VP of Alibaba Cloud, GM of Alibaba Cloud Server Infrastructure. "The UALink consortium, as a leader in the interconnect field of AI accelerators, has brought together key members from the AI infrastructure industry to work together to define interconnect protocol which is natively designed for AI accelerators, driving innovation in AI infrastructure. This will strongly promote the innovation of AI infrastructure and improve the execution efficiency of AI workloads, contributing to the establishment of an open and innovative industry ecosystem."

The Apple M4 hardly needs any introduction - the latest desktop-class SoC from the Cupertino giant is remarkably fast, while being impressively efficient. Its recently unveiled Pro and Max variants are equally praiseworthy, although none of the 4th generation Apple Silicon goodness is available on the extremely popular MacBook Air as of right now. However, that is about to change soon according to a reliable recent report.

According to Bloomberg's Mark Gurman, the M4-powered MacBook Air has already entered production, and is scheduled to witness the light of day by the spring of next year, possibly even earlier. However, it is certainly worth noting that unlike the MacBook Pro, the MacBook Air does not feature active cooling, making its performance rather limited in demanding, sustained scenarios as compared to the MacBook Pro. Even then, the M4 is likely to be much snappier than its primary x86 rival, Intel's Lunar Lake, if the M4 iPad Pro's performance is anything to go by.

Alphawave Semi (LSE: AWE), a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, proudly introduces the industry's first 64 Gbps Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) IP Subsystem to deliver unprecedented chiplet interconnect data rates, setting a new standard for ultra-high-performance D2D connectivity solutions in the industry. The third generation, 64 Gbps IP Subsystem builds on the successes of the most recent Gen 2 36 Gbps IP subsystem and silicon-proven Gen 1 24 Gbps and is available in TSMC's 3 nm Technology for both Standard and Advanced packaging. The silicon proven success and tapeout milestones pave the way for Alphawave Semi's Gen 3 UCIe IP subsystem offering.

Alphawave Semi is set to revolutionize connectivity with its Gen 3 64 Gbps UCIe IP, delivering a bandwidth density of over 20 Tbps/mm, with ultra-low power and latency. This solution is highly configurable supporting multiple protocols, including AXI-4, AXI-S, CXS, CHI and CHI-C2C to address the growing demands for high-performance connectivity across disaggregated systems in High-Performance Computing (HPC), Data Centers, and Artificial Intelligence (AI) applications.

Silicon Box, a global leader in advanced semiconductor packaging and system integration, welcomes the European Commission's approval of approximately €1.3 billion for its new manufacturing facility in Italy. The project, representing a total investment of €3.2 billion, will create 1,600 high-skilled jobs and establish Europe's most advanced semiconductor packaging facilities.

The investment supports the EU's strategic goal to produce 20% of the world's semiconductors by 2030 and marks Silicon Box's first expansion beyond Singapore. With its proprietary large format panel-level process lines, the factory can scale up the packaging of chips 6 to 8 times more than traditional wafer-level packaging.

The U.S. Department of Commerce will award GlobalWafers America and MEMC, LLC, U.S. subsidiaries of Taiwan-based GlobalWafers Co., Ltd., up to $406 million in direct funding under the CHIPS Incentives Program's Funding Opportunity for Commercial Fabrication Facilities.

The award will support planned investments of $4 billion in advanced semiconductor wafer manufacturing facilities in Sherman, Texas and St. Peters, Missouri. The Department will disburse the funds based on GWA's and MEMC's completion of project milestones over a multi-year timeframe.

The RPCS3 team has announced the successful implementation of arm64 architecture support for their PlayStation 3 emulator. This development enables the popular emulator to run on a broader range of devices, including Apple Silicon machines, Windows-on-Arm, and even some smaller Arm-based SBC systems like the Raspberry Pi 5. The journey to arm64 support began in late 2021, following the release of Apple's M1 processors, with initial efforts focused on Linux platforms. After overcoming numerous technical hurdles, the development team, led by core developer Nekotekina and graphics specialist kd-11, achieved a working implementation by mid-2024. One of the primary challenges involved adapting the emulator's just-in-time (JIT) compiler for arm64 systems.

The team developed a solution using LLVM's intermediate representation (IR) transformer, which allows the emulator to generate code once for x86-64 and then transform it for arm64 platforms. This approach eliminated the need to maintain separate codebases for different architectures. A particular technical challenge emerged from the difference in memory management between x86 and arm64 systems. While the PlayStation 3 and traditional x86 systems use 4 KB memory pages, modern arm64 platforms typically operate with 16 KB pages. Though this larger page size can improve memory performance in native applications, it presented unique challenges for emulating the PS3's graphics systems, particularly when handling smaller textures and buffers. While the emulator now runs on arm64 devices, performance varies significantly depending on the hardware. Simple applications and homebrew software show promising results, but more demanding commercial games may require substantial computational power beyond what current affordable Arm devices can provide.

AMD today announced the expansion of the AMD Versal adaptive system-on-chip (SoC) portfolio with the introduction of the Versal RF Series that includes the industry's highest compute performance in a single-chip device with integrated direct radio frequency (RF)-sampling data converters.

Versal RF Series offers precise, wideband-spectrum observability and up to 80 TOPS of digital signal processing (DSP) performance in a size, weight, and power (SWaP)-optimized design, targeting RF systems and test equipment applications in the aerospace and defense (A&D) and test and measurement (T&M) markets, respectively.

Quobly, a leading French quantum computing startup, has reported that FD-SOI technology can serve as a scalable platform for commercial quantum computing, leveraging traditional semiconductor manufacturing fabs and CEA-Leti's R&D pilot line.

The semiconductor industry has played a pivotal role in enabling classical computers to scale at cost; it has the same transformative potential for quantum computers, making them commercially scalable and cost competitive. Silicon spin qubits are excellent for achieving fault-tolerant, large-scale quantum computing, registering clock speeds in the µsec range, fidelity above 99% for one and two-qubit gate operations and incomparably small unit cell sizes (in the hundredths of 100 nm²).

During the prestigious IEDM 2024 conference, NVIDIA presented its vision for the future AI accelerator design, which the company plans to chase after in future accelerator iterations. Currently, the limits of chip packaging and silicon innovation are being stretched. However, future AI accelerators might need some additional verticals to gain the required performance improvement. The proposed design at IEDM 24 introduces silicon photonics (SiPh) at the center stage. NVIDIA's architecture calls for 12 SiPh connections for intrachip and interchip connections, with three connections per GPU tile across four GPU tiles per tier. This marks a significant departure from traditional interconnect technologies, which in the past have been limited by the natural properties of copper.

Perhaps the most striking aspect of NVIDIA's vision is the introduction of so-called "GPU tiers"—a novel approach that appears to stack GPU components vertically. This is complemented by an advanced 3D stacked DRAM configuration featuring six memory units per tile, enabling fine-grained memory access and substantially improved bandwidth. This stacked DRAM would have a direct electrical connection to the GPU tiles, mimicking the AMD 3D V-Cache on a larger scale. However, the timeline for implementation reflects the significant technological hurdles that must be overcome. The scale-up of silicon photonics manufacturing presents a particular challenge, with NVIDIA requiring the capacity to produce over one million SiPh connections monthly to make the design commercially viable. NVIDIA has invested in Lightmatter, which builds photonic packages for scaling the compute, so some form of its technology could end up in future NVIDIA accelerators

Today at the IEEE International Electron Devices Meeting (IEDM) 2024, Intel Foundry unveiled new breakthroughs to help drive the semiconductor industry forward into the next decade and beyond. Intel Foundry showcased new material advancements that help improve interconnections within a chip, resulting in up to 25% capacitance by using subtractive ruthenium. Intel Foundry also was first to report a 100x throughput improvement using a heterogeneous integration solution for advanced packaging to enable ultra-fast chip-to-chip assembly. And to further drive gate-all-around (GAA) scaling, Intel Foundry demonstrated work with silicon RibbonFET CMOS and with gate oxide module for scaled 2D FETs for improved device performance.

"Intel Foundry continues to help define and shape the roadmap for the semiconductor industry. Our latest breakthroughs underscore the company's commitment to delivering cutting-edge technology developed in the U.S., positioning us well to help balance the global supply chain and restore domestic manufacturing and technology leadership with the support of the U.S. CHIPS Act," says Sanjay Natarajan, Intel senior vice president and general manager of Intel Foundry Technology Research.

Chinese semiconductor memory giant YMTC is reportedly manufacturing anywhere between 400-500,000 wafers per year of leading-edge NAND memory, all on domestically produced wafers. According to Mayuki Hashimoto, CEO and Chairman of SUMCO, a Japanese company supplying raw silicon ingots and polished wafers, they are seeing a significant business impact stemming from China's growing self-reliance, especially with companies like YMTC producing its own silicon ingots and polished wafers. This has led to SUMCO's decreasing revenue, where the CEO shared some insights about Chinese ambitions. He added that China is producing about one million wafers of silicon per year, most of which are test wafers. This includes test runs from companies like SMIC and its customers, such as T-Head, HiSilicon, and others.

Last year, YMTC, with its Xtacking 4.0 3D NAND flash architecture, was the first company to achieve a 200+ layer count in the 3D NAND space. The company's product, X4-9070, a 232-layer TLC 3D NAND, uses multiple silicon wafers, hence growing its massive consumption of silicon that is projected to reach 500,000 wafers per year. Given that this is all homegrown silicon from ingots to NAND, this is a massive success for Chinese self-reliance efforts but a huge blow to companies that used to supply Chinese firms with raw materials. Although the company uses custom silicon, it still relies on foreign tools, photoresists, and pre-cursors. There are some indications that YMTC is developing its own tools; it is a plan of a broader strategy in the Chinese semiconductor industry to develop every step of the semiconductor manufacturing process. Huawei is also there to develop EUV scanners, and YMTC could help with its memory business, which is in need of a new tool.

Worldwide silicon wafer shipments increased 5.9% quarter-over-quarter to 3,214 million square inches (MSI) in the third quarter of 2024 and registered 6.8% growth from the 3,010 million square inches recorded during the same quarter last year, the SEMI Silicon Manufacturers Group (SMG) reported in its quarterly analysis of the silicon wafer industry.

"The third quarter wafer shipment results continued the upward trend which started in the second quarter of this year," said Lee Chungwei (李崇偉), Chairman of SEMI SMG and Vice President and Chief Auditor at GlobalWafers. "Inventory levels have declined throughout the supply chain but generally remain high. Demand for advanced wafers used for AI continues to be strong. However, the silicon wafer demand for automotive and industrial uses continues to be muted, while the demand for silicon used for handset and other consumer products has seen some areas of improvement. As a result, 2025 is likely to continue upward trends, but total shipments are not yet expected to return to the peak levels of 2022."

According to DigiTimes, NVIDIA is reportedly targeting the high-end segment for its first consumer CPU attempt. Slated to arrive in 2025, NVIDIA is partnering with MediaTek to break into the AI PC market, currently being popularized by Qualcomm, Intel, and AMD. With Microsoft and Qualcomm laying the foundation for Windows-on-Arm (WoA) development, NVIDIA plans to join and leverage its massive ecosystem of partners to design and deliver regular applications and games for its Arm-based processors. At the same time, NVIDIA is also scheduled to launch "Blackwell" GPUs for consumers, which could end up in these AI PCs with an Arm CPU at its core.

NVIDIA's partner, MediaTek, has recently launched a big core SoC for mobile called Dimensity 9400. NVIDIA could use something like that as a base for its SoC and add its Blackwell IP to the mix. This would be similar to what Apple is doing with its Apple Silicon and the recent M4 Max chip, which is apparently the fastest CPU in single-threaded and multithreaded workloads, as per recent Geekbench recordings. For NVIDIA, the company already has a team of CPU designers that delivered its Grace CPU to enterprise/server customers. Using off-the-shelf Arm Neoverse IP, the company's customers are acquiring systems with Grace CPUs as fast as they are produced. This puts a lot of hope into NVIDIA's upcoming AI PC, which could offer a selling point no other WoA device currently provides, and that is tried and tested gaming-grade GPU with AI accelerators.

After announcing the world's first 300-millimeter gallium nitride (GaN) power wafer and opening the world's largest 200-millimeter silicon carbide (SiC) power fab in Kulim, Malaysia, Infineon Technologies AG has unveiled the next milestone in semiconductor manufacturing technology. Infineon has reached a breakthrough in handling and processing the thinnest silicon power wafers ever manufactured, with a thickness of only 20 micrometers and a diameter of 300 millimeters, in a high-scale semiconductor fab. The ultra-thin silicon wafers are only a quarter as thick as a human hair and half as thick as current state-of-the-art wafers of 40-60 micrometers.

"The world's thinnest silicon wafer is proof of our dedication to deliver outstanding customer value by pushing the technical boundaries of power semiconductor technology," said Jochen Hanebeck, CEO at Infineon Technologies. "Infineon's breakthrough in ultra-thin wafer technology marks a significant step forward in energy-efficient power solutions and helps us leverage the full potential of the global trends decarbonization and digitalization. With this technological masterpiece, we are solidifying our position as the industry's innovation leader by mastering all three relevant semiconductor materials: Si, SiC and GaN."

Ultra Accelerator Link (UALink ) Consortium, led by Board Members from AMD, Amazon Web Services (AWS), Astera Labs, Cisco, Google, Hewlett Packard Enterprise (HPE), Intel, Meta and Microsoft, have announced the incorporation of the Consortium and are extending an invitation for membership to the community. The UALink Promoter Group was founded in May 2024 to define a high-speed, low-latency interconnect for scale-up communications between accelerators and switches in AI pods & clusters. "The UALink standard defines high-speed and low latency communication for scale-up AI systems in data centers"

The American semiconductor landscape reached a significant milestone as TSMC's new Arizona manufacturing facility demonstrated remarkable production efficiency, exceeding its Taiwanese counterparts by 4% in yield rates. This achievement, revealed at a recent industry webinar by the company's US division chief, represents a major step forward in America's push to strengthen domestic chip manufacturing capabilities. Since initiating its 4 nm node production operations this spring, the Phoenix-based facility has demonstrated impressive technical proficiency, achieving production standards that match and surpass TSMC's established Taiwanese facilities. The project, backed by substantial federal support, including $11.6 billion in combined grants and loans plus significant tax incentives, aims to establish three cutting-edge manufacturing plants in Arizona.

The company's global leadership praised the facility's performance, noting its strategic importance in demonstrating TSMC's ability to maintain exceptional manufacturing standards across international locations. This success carries particular weight given the project's earlier hurdles, which included workforce challenges and timeline adjustments that shifted the entire production schedule by approximately one year. This development gains additional significance against industry-wide challenges, particularly as competitors like Intel and Samsung face operational and financial obstacles. The semiconductor giant's plans now extend to potential further expansion, with the Phoenix site capable of hosting up to six manufacturing facilities. Future growth prospects could be enhanced by proposed additional government initiatives supporting domestic chip production.

Global shipments of silicon wafers are projected to decline 2% in 2024 to 12,174 million square inches (MSI) with a strong rebound of 10% delayed until 2025 to reach 13,328 MSI as wafer demand continues to recover from the downcycle, SEMI reported today in its annual silicon shipment forecast.

Strong silicon wafer shipment growth is expected to continue through 2027 to meet increasing demand related to AI and advanced processing, driving improved fab utilization rate for global semiconductor production capacity. Moreover, new applications in advanced packaging and high-bandwidth memory (HBM) production, which require additional wafers, are contributing to the rising need for silicon wafers. Such applications include temporary or permanent carrier wafers, interposers, device separation into chiplets, and memory/logic array separation.

Recent reports from South China Morning Post unveil developments in China's semiconductor industry, with significant progress in two critical areas: advanced memory chips and silicon photonics. These breakthroughs mark important steps in the country's pursuit of technological self-reliance amid global trade tensions. In Wuhan, a startup called Numemory has unveiled a new storage-class memory (SCM) chip. The "NM101" chip boasts an impressive 64 GB capacity, far surpassing the megabyte-range offerings currently dominating the market. This novel chip blends the strengths of traditional DRAM and NAND flash storage, delivering rapid, non-volatile, persistent memory ideal for server and data center applications. The NM101's design prioritizes high capacity, density, and bandwidth while maintaining low latency. These characteristics make it particularly well-suited for data centers and cloud computing infrastructures. Initial reports suggest that storage devices incorporating this SCM technology can write an entire 10 GB high-definition video file in a mere second.

Concurrently, another Wuhan-based institution, JFS Laboratory, has achieved a milestone in silicon photonics research. The state-backed facility successfully merged a laser light source with a silicon chip, a feat previously unrealized in China. This innovation in silicon photonics leverages light signals for data transmission, potentially circumventing the looming physical constraints of traditional electric signal-based chip designs. This accomplishment is viewed as addressing a crucial gap in China's optoelectronics capabilities, which used to lag behind Western chip designers and startups. Using silicon photonics, infrastructure scale-out can be sustained on a much larger scale without significant power consumption increase. While these developments represent significant progress, it's important to note that bridging the gap between laboratory breakthroughs and mass-produced, commercially viable products remains a substantial challenge. The path from research success to market dominance is often long and complex, requiring sustained investment and further technological refinement.

Alphawave Semi, a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, has launched the industry's first 3 nm successful silicon bring-up of Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) IP with TSMC's Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology.

The complete PHY and Controller subsystem was developed in collaboration with TSMC and targets applications such as hyperscaler, high-performance computing (HPC) and artificial intelligence (AI).

Dr. Larry Zu, Founder and CEO of Sarcina Technology, the Application Specific Advanced Packaging (ASAP) Design Service and Production leader, predicted that recent Bump Pitch Transformer (BPT) designs will speed 2.5D IC advanced packaging adoption to meet the red-hot demand for AI innovation. In remarks made in the Keysight Theater at the 61st Design Automation Conference, he envisioned new BPT technology paving the way for new artificial intelligence computing opportunities.

"We believe that the Bump Pitch Transformer architecture will accelerate the growth rate of 2.5D semiconductor packages that are key to meeting the explosive demand for AI-driven computing capabilities," Dr. Zu said during his address in the Keysight Theater.

STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, announces a new high-volume 200 mm silicon carbide ("SiC") manufacturing facility for power devices and modules, as well as test and packaging, to be built in Catania, Italy. Combined with the SiC substrate manufacturing facility being readied on the same site,these facilities will form ST's Silicon Carbide Campus, realizing the Company's vision of a fully vertically integrated manufacturing facility for the mass production of SiC on one site.The creation of the new Silicon Carbide Campus is a key milestone to support customers for SiC devices across automotive, industrial and cloud infrastructure applications, as they transition to electrification and seek higher efficiency.

"The fully integrated capabilities unlocked by the Silicon Carbide Campus in Catania will contribute significantly to ST's SiC technology leadership for automotive and industrial customers through the next decades," said Jean-Marc Chery, President and Chief Executive Officer of STMicroelectronics. "The scale and synergies offered by this project will enable us to better innovate with high-volume manufacturing capacity, to the benefit of our European and global customers as they transition to electrification and seek more energy efficient solutions to meet their decarbonization goals."

Yesterday, Apple launched its next-generation M4 chip based on Apple Silicon custom design. The processor is a fourth-generation design that brings AI capabilities and improved CPU performance. First debuting in an iPad Pro, the CPU has been benchmarked in Geekbench v6. And results seem to be very promising. The latest M4 chip managed to score 3,767 points in single-core tests and 14,677 points in multi-core tests. Compared to the M3 chip, which scores 3,087 points in single-core and 11,702 in multi-core tests, the M4 chip is about 22% faster in single-core and 25% faster in multi-core synthetic benchmarks.

Of course, these results are not real-world use cases, but they give us a hint of what the Apple Silicon design team has been working on. For real-world results, we have to wait a little longer to see reviews and results from devices such as MacBook Pro and MacBook Air, which should have better cooling and possibly better clocks for the chip.

A few months ago, we covered proof of overclocking an off-the-shelf 2.5-inch SATA III NAND Flash SSD thanks to Gabriel Ferraz, Computer Engineer and TechPowerUp's SSD database maintainer. Now, he is back with another equally interesting project of modifying a Quad-Level Cell (QLC) SATA III SSD into a Single-Level Cell (SLC) SATA III SSD. Using the Crucial BX500 512 GB SSD, he aimed at transforming the QLC drive into a more endurant and higher-performance SLC. Silicon Motion SM2259XT2 powers the drive of choice with a single-core ARC 32-bit CPU clocked at 550 MHz and two channels running at 800 MT/s (400 MHz) without a DRAM cache. This particular SSD uses four NAND Flash dies from Micron with NY240 part numbers. Two dies are controlled per channel. These NAND Flash dies were designed to operate at 1,600 MT/s (800 MHz) but are limited to only 525 MT/s in this drive in the real world.

The average endurance of these dies is 1,500 P/E cycles in NANDs FortisFlash and about 900 P/E cycles in Mediagrade. Transforming the same drive in the pSLC is bumping those numbers to 100,000 and 60,000, respectively. However, getting that to work is the tricky part. To achieve this, you have to download MPtools for the Silicon Motion SM2259XT2 controller from the USBdev.ru website and find the correct die used in the SSD. Then, the software is modified carefully, and a case-sensitive configuration file is modified to allow for SLC mode, which forces the die to run as a SLC NAND Flash die. Finally, firmware folder must be reached and files need to be moved arround in a way seen in the video.

While everyone has been focused on shipping an AI-enhanced product recently, one tech giant didn't appear to be bothered- Apple. However, according to Mark Gurman from Bloomberg, Apple is readying an overhaul of its Apple Silicon M-series chips to embed AI processing capabilities at the processor level. As the report indicates, Apple is preparing an update for late 2024 and early 2025 with the M4 series of chips, which will reportedly feature AI processing units similar to those found in other commercial chips. There should be three levels of the M4 series, with the entry-level M4 codenamed Donan, the mid-level M4 chip codenamed Brava, and the high-end M4 chip codenamed Hydra.

Sales of Apple Macs peaked in 2022; the following year was a sharp decline, and sales have continued to be flat since. The new AI PCs for Windows-based systems have been generating hype from all major vendors, hoping to introduce AI features to end users. However, Apple wants to be part of the revolution, and the company has already scheduled the World Wide Developer Conference for June 10th. At WWDC this year, Apple is supposed to show a suite of AI-powered solutions to enable better user experience and increase productivity. With M4 chips getting AI enhancement, the WWDC announcements will get extra hardware accelerations. However, we must wait for the exact announcements before making further assumptions.