Ahead of their October 7th product launch and November availability, we have confirmation of the specifications and pricing of Intel's 10th generation Core X "Cascade Lake-X" HEDT processors in the LGA2066 package. These chips feature compatibility with existing socket LGA2066 motherboards with a UEFI BIOS update, although several motherboard manufacturers are launching new products with some of the latest connectivity options, such as 2.5 GbE wired Ethernet, and 802.11ax Wi-Fi 6 WLAN.

The 10th generation Core X HEDT processor family is based on the new 14 nm++ "Cascade Lake" silicon, which comes with hardware fixes against several classes side-channel vulnerabilities, and introduces an updated instruction-set that includes more AVX-512 instructions, and the new DLBoost instruction. DLBoost leverages new fixed-function hardware on silicon to accelerate AI deep-learning neural-set building and training by up to 5 times. Intel's first wave of 10th gen Core X lineup is rather slim, with just four processor models. The company did away with the Core i7 brand extension, as core-counts in the mainstream desktop segment have already reached 8-core. The lineup now begins at 10-core/20-thread, with the chip's full 48-lane PCI-Express and 4-channel DDR4 interfaces enabled across the board. All models feature the "XE" brand extension, and feature unlocked base-clock multipliers.

As we are nearing the launch of USB4, which will feature Thunderbolt 3 like speeds of up to 40 Gbps, PCIe and DisplayPort support within USB-C form factor, there are already drivers showing up to support the new standard and ensure the launch and transition to the newest USB version will go smoothly.

According to the finds of Phoronix, Intel's open-source engineers have been working on a patch to support the new standard in the Linux kernel. Being based on Thunderbolt 3, the bring-up of USB4 isn't very difficult as it allows for a lot of code reuse, making things easier for kernel developers. Only 22 patches were submitted that resulted in under 4,000 lines of new code in total. For now, the support is in the stage of a pull request, so it should go mainstream very soon, most likely with the release of Linux kernel 5.5, if other features like power management are worked out soon.

Today, at a launch event in New York City, Microsoft previewed the Surface Neo, a category-defining device co-engineered with Intel. The dual-screen device will be powered by Intel's unique processor, code-named "Lakefield," that features an industry-first architecture combining a hybrid CPU with Intel's Foveros 3D packaging technology. It offers device-makers more flexibility to innovate on design, form factor and experience.

"The innovation we've achieved with Lakefield gives our industry partners the ability to deliver on new experiences, and Microsoft's Neo is trailblazing a new category of devices. Intel is committed to pushing the boundaries of computing by delivering key technology innovations for partners across the ecosystem," said Gregory Bryant, Intel executive vice president and general manager of the Client Computing Group.

Intel's STrategic Offensive Research & Mitigations (STORM) department, which the company set up back in 2017 when it learned of side-channel attack vulnerabilities in its CPUs, have penned a paper detailing a proposed solution to the problem. Intel's offensive security research team counts with around 60 workers who focus on proactive security testing and in-depth investigations. Of that group, STORM is a subset of around 12 individuals who specifically work on prototyping exploits to show their practical impact. The solution proposed by this group is essentially a new memory-based hardware fix, going by the name of SAPM (Speculative-Access Protected Memory). The new solution would implement a resistant hardware fix in the CPU's memory that essentially includes blocks for known speculative-access hacks, such as the ones that hit Intel CPUs hard such as Meltdown, Foreshadow, MDS, SpectreRSB and Spoiler.

For now, the proposed solution is only at a "theory and possible implementation options" level. It will take a long time for it to find its way inside working Intel CPUs - if it ever does, really, since for now, it's just a speculative solution. A multitude of tests have to be done in order for its implementation to be approved and finally etched into good old silicon. Intel's STORM says that the SAPM approach would carry a performance hit; however, the group also calculates it to be "potentially lesser" than the current impact of all released software mitigations. Since the solution doesn't address every discovered side-channel attack specifically, but addresses the type of back-end operations that concern these attacks, the team is confident this solution would harden Intel CPUs against (most of) both known and not-yet-known speculative execution hacks.

Intel is readying the i225-V "Foxville," its new generation of low-cost Ethernet PHY controllers for client-segment motherboards and notebooks. With it, the company will be mainstreaming 2.5 Gbps as the client-segment wired-networking standard, after nearly 15 years of 1 GbE dominance. The i225-V is expected to feature in the upcoming wave of socket LGA2066 motherboards for Intel's "Cascade Lake-X" HEDT processors, followed by the company's 400-series chipset that launches alongside the "Comet Lake-S" MSDT processors. The i225-V isn't the first of its kind, with the likes of Realtek and Broadcom having already launched 2.5 GbE PHYs. The Intel chip, however, is expected to mainstream the standard as it's currently the most popular GbE PHY brand with the success of the i219-V and i218-V.

Much like the i219-V, the i225-V is a low-cost PHY that relies on PCH-based Ethernet MAC and its proprietary PCIe-based bus that runs at half the data-rate of PCIe. This is precisely why the i219-V doesn't feature on AMD motherboards, but rather its pricier sibling, the i211-AT, which comes with an integrated MAC and a standard PCIe interface. Both chips are known to offer identical throughput performance, however, the i211-AT edges ahead with some features such as TCP segmentation, direct cache access, etc. The i219-V sells for as little as $1.5 per chip in high-volume reels to motherboard manufacturers, and the i225-V is expected to be priced roughly similar. In contrast, the i211-AT goes for almost $3.25 a pop. Intel is yet to publish documentation that details software features of the i225-V, but the Linux community is already on the job at developing drivers. 2.5 GbE uses existing Cat5E/Cat6 cabling requirements as 1 GbE, and hence has a better chance at mainstreaming compared to 10 GbE, which has been around for a decade, with little success in the client segment.

October 7 promises to be an action-packed day, with not just AMD's launch of its Radeon RX 5500 series graphics card, but also Intel's 10th generation Core X "Cascade Lake" HEDT processors in the LGA2066 package. With AMD having achieved near-parity with Intel on IPC, the focus with the 10th generation Core X will be on price-performance, delivering double the number of cores to the Dollar compared to the previous generation. Intel will nearly halve the "Dollars per core" metric of these processors down to roughly $57 per core compared to $103 per core of the 9th generation Core X. This means the 10-core/20-thread model that the series starts with, will be priced under $600.

The first wave of these processors will include the 10-core/20-thread Core i9-10900XE, followed by the 12-core/24-thread i9-10920XE around the $700-mark, the 14-core/28-thread i9-10940XE around the $800-mark, and the range-topping 18-core/28-thread i9-10960XE at $999, nearly half that of the previous-generation i9-9980XE. There is a curious lack of a 16-core model. These chips feature a 44-lane PCI-Express gen 3.0 root complex, a quad-channel DDR4 memory interface supporting up to 256 GB of DDR4-2933 memory (native speed), and compatibility with existing socket LGA2066 motherboards with a BIOS update. The chips also feature an updated AES-512 ISA, the new DLBoost instruction set with a fixed-function hardware that accelerates neural net training by 5 times, and an updated Turbo Boost Max algorithm. Intel will extensively market these chips to creators and PC enthusiasts. October 7 will see a paper-launch, followed by November market-availability.

The next big update to Windows 10, slated for some time later this year, will have awareness to "favored cores." This leverages the ability of some of the latest processors to tell the operating system which of its cores are marginally "better" than the other, so it could push more of its single-threaded workloads to that core, for the highest boost clocks. Not all cores on a multi-core processor die are created equal, due to minor variations in manufacturing. Intel processors featuring Turbo Boost Max 3.0, as well as AMD Ryzen processors, have the ability to tell the operating system which of its cores are "better" than the other, which core is the "best" on the die, which is the "best" in a particular CCX (in case of "Zen" chips), and so on.

The best cores on a silicon are called "favored cores," and proper OS-level optimization could improve performance on 1-4 threaded workloads by "up to 15 percent," according to Intel. This, however, requires the processor to support Turbo Boost Max 3.0, which currently only HEDT processors do in the Intel camp. Over in the AMD front, Microsoft introduced more awareness to the multi-CCX and multi-die design of "Zen" processors with Windows 10 1903, and schedules workloads to make the most out of Zen's multi-core topology. "Zen" processors are able to report their best cores per CCX, per die, and per package, and the Ryzen Master software already displays this information, however, Windows hasn't been able to exploit favored cores. This will change with the upcoming major Windows 10 update.

Karen Walker, a veteran of more than 20 years of global technology industry marketing, will join Intel as senior vice president and chief marketing officer (CMO), effective Oct. 23. Walker will oversee Intel's global marketing group and be responsible for building and strengthening Intel's brand, supporting growth strategies, cultivating opportunities in new and existing markets, and increasing demand for Intel's products and solutions globally.

"Karen is a truly world-class CMO," said Bob Swan, Intel's CEO. "She has deep experience with many of our most valued customers and a keen understanding of what it will take to play an even larger role in their success. We are excited to have Karen on our leadership team."

Intel's upcoming Gen12 iGPU solutions are being touted as sporting Intel's greatest architecture shift in their integrated graphics technologies in a decade. For one, each Execution unit will be freed of the additional workload of having to guarantee data coherency between register reads and writes - that work is being handed over to a reworked compiler, thus freeing up cycles that could be better spent processing triangles. But of course, there are easier ways to improve a GPU's performance without extensive reworks of their design (as AMD and NVIDIA have shown us time and again) - simply by increasing the number of execution units. And it seems Intel is ready to do just that with their Gen12 as well.

An unidentified Intel Gen12 iGPU was benchmarked in CompuBench, and the report includes interesting tidbits, such as the number of Execution Units - 96, a vast increase over Intel's most powerful iGPU to date, the Iris Pro P580, with its 72 EU - and far, far away from the consumer market's UHD 630 and its 24 EUs. The Gen12 iGPU that was benchmarked increases the EU count by 33% compared to Intel's top performing iGPU - add to that performance increases through the "extensive architecture rework", and we could be looking at an Intel iGPU part that achieves some 40% (speculative) better performance than their current best performer. The part was clocked at 1.1 GHz - and the Iris Pro P580 also clocked to that maximum clock under the best Boost conditions. Let's see what next-gen Intel has in store for us, shall we?

"Moore's Law" is a term coined in 1965 by Gordon Moore, who presented a paper which predicts that semiconductor scaling will allow integrated circuits to feature twice as many transistors present per same area as opposed to a chip manufactured two years ago. That means we could get same performance at half the power than the previous chip, or double the performance at same power/price in only two years time. Today we'll investigate if Moore's Law stayed true to its cause over the years and how much longer can it keep going.

Australian e-tailer MWave has put up their product page for the Intel Core i9-9900KS processor that Intel announced earlier this year, but with no actual product in sight. The merchant's listing is showing an AUD 899 price for SKU BX80684I99900KS, which converts to USD 605. The new Intel processor, is basically a binned eight-core Coffee Lake Core i9-9900K, which runs at 4.0 GHz base clock (up by 400 MHz) and 5.0 GHz all-core Turbo (300 MHz increase). Single-core maximum Turbo remains at 5.0 GHz (just like on the Core i9-9900K).

Just earlier this week, ASUS posted a BIOS update note, mentioning in it that the Core i9-9900KS will have a 127 W TDP. It looks like Intel can definitely defend the gaming performance crown with the Core i9-9900KS, mostly thanks to its high clock speeds. However, since most of the improvements are in multi-core workload boost clocks, and single-threaded clocks are identical to 9900K, I'm having some doubts whether the processor can really make any substantial difference — it's definitely not going to beat the $100 cheaper Ryzen 9 3900X in Cinebench, and the 127 W TDP limit might mean that the 5.0 GHz all-core Boost will end up being active only for a short amount of time.

Intel today at a press event in South Korea announced their plans for future product launches in the memory spaces. Optane is the name of the carriage Intel is pulling here - there's no novelty about that - and the company will be pushing a second generation release of Optane enterprise SSDs and Optane DC Persistent Memory modules. Most interesting for us down-to-earth PC enthusiasts, though - the market launch of 144 Layer QLC NAND in 2020, which should bring even lower pricing to NAND-based devices. Later, the company also plans to launch 144 layer TLC NAND solutions.

The new Optane modules apparently make use of first-generation 3D XPoint memory still - the love child of the now defunct Intel-Micron partnership. Intel's new Optane DC Persistent Memory products will materialize in codename Barlow Pass modules, with a release window around the likes of Cooper Lake (14nm) and Ice Lake (10nm) server processors scheduled for 2020. It seems that Intel's only consumer solution based in Optane - the Optane Memory H10 two-in-one SSD - is a lonely child effort which won't be joined by the previously-planned Optane Memory M15 (a dedicated cache drive for systems with mechanical-based storage, which are already on their way out) and Optane SSD 815P (which would only offer 118 GB of storage, clearly too little for current data storing trends in the overall market.

Shuttle is expanding its successful XPC all-in-one range, which now comprises four different platforms, to include a model based on Intel's Whiskey Lake processor generation. In addition to the 15.6" capacitive touchscreen, the P51U also features an IP54-certified front panel. The display has Full HD resolution, while an energy-saving Intel Celeron 4205U dual-core processor delivers the required computing power.

Alongside the X50, the P51U is the second Shuttle model in a 15.6" format. It is the first of its size with a capacitive IPS display that has a resolution of 1920×1080 pixels and allows easy, intuitive operation using more than one finger. Its compact dimensions of 39.3×27.3×4.0 cm (W×H×D) mean that it fits easily into a range of different environments. The P51U is less at home in the consumer segment than in the POS segment. The retail sector and restaurant trade are two primary target groups for this all-in-one PC.

Intel is constantly having troubles with its silicon manufacturing business lately. Firstly the late delivery of 10 nm, then the shortage of 14 nm chips that started all the way back in 2018. Despite the making of $1 Billion investment into extending its 14 nm production capacity, there seems to be no end of troubles in sight.

According to sources close to DigiTimes, 14 nm production has fallen short of demand again and will likely cause many notebook manufacturers to delay their products to 2020. Most likely victim of this delay is the newly announced 10th generation mobile CPUs codenamed Comet Lake. Those CPUs were supposed to be built using Intel's "14nm++" revision of 14 nm technology which targets higher CPU frequencies and improved efficiency, but most likely due to continued shortage of 14nm, there will be only a few notebooks powered by these chips. As the source suggests, many manufacturers are likely to delay the launch of their products to 2020, when this situation is supposed to be resolved.

Intel's upcoming 5 GHz-on-all-cores Core i9-9900KS will certainly be a beast of a processor for the company - in more ways than one. The 8-core, 16-thread 5 5 GHz all-core turbo CPU will be Intel's best-performing consumer CPU for a while. The steps taken to ensure that have been the only ones Intel could do with their current CPU design and fabrication process - increase the TDP and improve all-core boost frequency, which should allow the CPU to perform incredibly well in peak performance.

The question that remains, of course, is how long the CPU will actually be able to keep its 5.0 GHz all-core frequency when it's engaged. The 127 W TDP as outed by an ASUS BIOS is a monstrous amount for an 8-core CPU, and I don't envy the heatsinks that will have to keep it in check. All in all, this seems to be nothing more than a CPU binned for Intel's purposes of becoming the best CPU for gaming and "home user relevant applications".

Intel's upcoming Extreme Edition Core i9-10980XE from the Cascade Lake-X family. Cascade Lake-X (CSL-X) will be Intel's next take on the High End Desktop (HEDT) systems. The Core i9-10980XE is pegged as the flagship on that lineup, sporting an 18-core, 36-thread design, and are still based on Intel's 14 nm process node. These processors will be pin-compatible with Intel's LGA 2066 platform. Caches are expected to be set at 1.125 MB, 18 MB and 24.75 MB of L1, L2 and L3.

Base clocks set in the Geekbench 4 entry are set at 4.1 GHz, with a maximum boost of 4.7 GHz. That's a lot of frequency on a 14 nm CPU with 18 cores; if previous entries on the Intel HEDT family (such as the i9-9980XE) sported a 165 W TDP with clocks of 3.0 GHz and 4.4 GHz respectively, it seems highly unlikely that Intel will keep the same TDP for the i9-10980XE - and even if they do, power consumption will certainly be higher. Those reported clocks for the i9-10980XE may not be right, however - we don't know the conditions of the test run.

AMD just released an update on their upcoming processor launches this year. First revealed at E3, just a few months ago, the Ryzen 9 3950X is the world's first processor to bring 16-cores and 32-threads to the consumer desktop space. The processor's boost clock is rated at "up to 4.7 GHz", which we might now actually see, thanks to an updated AGESA software that AMD released earlier this month. Base clock for this $749 processor is set at 3.5 GHz, and TDP is 105 W, with 72 MB cache. While AMD said "September" for Ryzen 9 3950X back at E3, it looks like the date got pushed back a little bit, to November, which really makes no difference, in the grand scheme of things.

The second big part of today's announcement is that AMD is indeed working on "Rome"-based third generation Threadripper processors (probably the industry's worst-kept secret), and that these CPUs will also be launching in November, right in time to preempt Intel from having any success with their upcoming Cascade Lake-X processors. Official information on AMD's new HEDT lineup is extremely sparse so far, but if we go by recent leaks, then we should expect new chipsets and up to 32-cores/64-threads.AMD's full statement is quoted below.

Today, Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, Intel Corporation and Microsoft announce the incorporation of the Compute Express Link (CXL) Consortium, and unveiled the names of its newly-elected members to its Board of Directors. The core group of key industry partners announced their intent to incorporate in March 2019, and remain dedicated to advancing the CXL standard, a new high-speed CPU-to-Device and CPU-to-Memory interconnect which accelerates next-generation data center performance.

The five new CXL board members are as follows: Steve Fields, Fellow and Chief Engineer of Power Systems, IBM; Gaurav Singh, Corporate Vice President, Xilinx; Dong Wei, Standards Architect and Fellow at ARM Holdings; Nathan Kalyanasundharam, Senior Fellow at AMD Semiconductor; and Larrie Carr, Fellow, Technical Strategy and Architecture, Data Center Solutions, Microchip Technology Inc.

With its 10th generation Core X "Cascade Lake-X" HEDT processor series, Intel will not bother designing models with single-digit core-counts. The series is likely to start at 10 cores with the Core i9-10900X. This 10-core/20-thread processor features a quad-channel DDR4 memory interface, and comes with clock speeds of 3.70 GHz base, a 200 MHz speed-bump over the Core i9-9900X. The chip retains the mesh interconnect design and cache hierarchy of Intel's HEDT processors since "Skylake-X," with 1 MB of dedicated L2 cache per core, and 19.3 MB of shared L3 cache.

Geekbench tests run on the chip show it to perform roughly on par with the i9-9900X, with the 200 MHz speed-bump expected to marginally improve multi-threaded performance. Where the "Cascade Lake-X" silicon is expected to one-up "Skylake-X" is its support for DLBoost, an on-die fixed function hardware that multiplies matrices, improving AI DNN building and training; and pricing. Intel is expected to price its next-generation HEDT processors aggressively, to nearly double cores-per-Dollar.

InstLatX64 has posted a CPU dump of Intel's next-generation 10 nm CPUs codenamed Tiger Lake. With the CPUID of 806C0, this Tiger Lake chip runs at 1000 MHz base and 3400 MHz boost clocks which is lower than the current Ice Lake models, but that is to be expected given that this might be just an engineering sample, meaning that production/consumer revision will have better frequency.

Perhaps one of the most interesting findings this dump shows is the new L3 cache configuration. Up until now Intel usually put 2 MB of L3 cache per each core, however with Tiger Lake, it seems like the plan is to boost the amount of available cache. Now we are going to get 50% more L3 cache resulting in 3 MB per core or 12 MB in total for this four-core chip. Improved cache capacity can result in additional latency because of additional distance data needs to travel to get in and out of cache, but Intel's engineers surely solved this problem. Additionally, full AVX512 support is present except avx512_bf which supports bfloat16 floating-point variation found in Cooper Lake Xeons.

The Wi-Fi CERTIFIED 6 certification program from Wi-Fi Alliance is now available and delivers the best user experience with devices based on IEEE 802.11ax. The certification program brings new features and capabilities that enable substantially greater overall Wi-Fi network performance in challenging environments with many connected devices such as stadiums, airports, and industrial parks. With adoption of the latest Wi-Fi generation increasing, product vendors and service providers can trust Wi-Fi CERTIFIED will distinguish Wi-Fi 6 products and networks that meet the highest standards for security and interoperability. Wi-Fi CERTIFIED 6 provides significant capacity, performance, and latency improvements to the entire Wi-Fi ecosystem, while ensuring products across vendors to work well together to deliver greater innovation and opportunity.

Wi-Fi CERTIFIED 6 supports a more diverse set of devices and applications, from those requiring peak performance in demanding enterprise environments to those requiring low power and low latency in smart homes or industrial IoT scenarios. Wi-Fi CERTIFIED 6 delivers nearly four times the capacity of Wi-Fi 5, and is an evolutionary advancement for Wi-Fi's ability to deliver high-performance infrastructure and optimized connectivity to all devices on a network simultaneously - bringing noticeable improvements in densely connected Wi-Fi environments. Wi-Fi CERTIFIED 6 delivers critical connectivity that supports cellular networks, and leverages high speeds, low latency, power efficiency, greater capacity, and enhanced coverage to deliver many advanced 5G services.

Microsoft has been using Intel hardware exclusively on its Surface lineup ever since it came out with the first Surface device. The choice was clear - Intel offered much better energy efficiency than anything AMD could offer at the time, besides the strong bond between the two companies. However, it seems that AMD might have done enough with its Ryzen 3000 series to sway big Microsoft into using some of its hardware (Ryzen 3000H or U) on upcoming Surface devices, if reports are to be believed.

Microsoft should be refreshing its Surface Laptop 2 with a 15-inch variant packing AMD hardware. It's uncertain if this will happen, and much less likely to happen for the entirety of Microsoft's Surface product stack (which includes potential refreshes for Surface Pro 6, Surface Book 2, Surface Go or Surface Studio 2). However, that AMD is now being considered alongside Intel in what can be said to be the ultimate Windows experience in Microsoft's usually excellently-designed products is a prestige in and of itself, and means an empowered brand standing for the red camp. Oh and Microsoft might finally be introducing that dual-screen device we've been hearing rumblings about for a while. Project "Centaurus" has already been seeded among Intel insiders, it seems, so it might see the light of day in the upcoming Microsoft Surface event taking place in New York on October 2nd.

MAINGEAR — an award-winning PC system integrator of custom gaming desktops, notebooks, and workstations — today launched the MAINGEAR ELEMENT, their new ultimate gaming notebook designed in collaboration with Intel. Custom engineered from the ground up, the ELEMENT features best-in-class hardware housed in a sleek machined magnesium alloy body, making it MAINGEAR's most professional notebook ever released.

The all-new ELEMENT fuses MAINGEAR's passion for design and performance into a truly modern gaming notebook with a thin, minimalist profile that doesn't compromise on raw power. The ELEMENT is optimized for the most demanding gamers and content creators, pairing a 9th Gen Intel i7-9750H processor and an NVIDIA GeForce RTX 2070 with Max-Q design GPU to hit peak performance in today's latest games. An ultra-smooth 144hz 15.6" IPS display with a narrow bezel delivers an incredibly immersive gaming experience. An RGB keyboard with individually-lit silent mechanical switches and a glass touchpad ensure users have precise control of the on-screen action. 32 GB of DDR4 memory and 2 TB of blazing-fast NVMe storage top off the ELEMENT's high-end specs.

Intel is slowly realizing plans to "one up" its GPU game starting from first 10 nm Ice Lake CPUs that feature Gen11 graphics, equipping users of integrated GPUs with much more performance than they previously got. Fortunately, Intel doesn't plan to stop there. Thanks to the recent pull request found on GitLab Mesa repository, we can now expect to receive biggest GPU performance bump in over a decade with the arrival of Gen12 based GPUs, found on next generation Tiger Lake processors.

In this merge request, Francisco Jerez, member of Intel's open source Linux graphics team, stated the following: "Gen12 is planned to include one of the most in-depth reworks of the Intel EU ISA since the original i965. The encoding of almost every instruction field, hardware opcode and register type needs to be updated in this merge request. But probably the most invasive change is the removal of the register scoreboard logic from the hardware, which means that the EU will no longer guarantee data coherency between register reads and writes, and will require the compiler to synchronize dependent instructions anytime there is a potential data hazard..."

DDIO, or Direct Data I/O, is an Intel-exclusive performance enhancement that allows NICs to directly access a processor's L3 cache, completely bypassing the a server's RAM, to increase NIC performance and lower latencies. Cybersecurity researchers from the Vrije Universiteit Amsterdam and ETH Zurich, in a research paper published on Tuesday, have discovered a critical vulnerability with DDIO that allows compromised servers in a network to steal data from every other machine on its local network. This include the ability to obtain keystrokes and other sensitive data flowing through the memory of vulnerable servers. This effect is compounded in data centers that have not just DDIO, but also RDMA (remote direct memory access) enabled, in which a single server can compromise an entire network. RDMA is a key ingredient in shoring up performance in HPCs and supercomputing environments. Intel in its initial response asked customers to disable DDIO and RDMA on machines with access to untrusted networks, while it works on patches.

The NetCAT vulnerability spells big trouble for web hosting providers. If a hacker leases a server in a data-center with RDMA and DDIO enabled, they can compromise other customers' servers and steal their data. "While NetCAT is powerful even with only minimal assumptions, we believe that we have merely scratched the surface of possibilities for network-based cache attacks, and we expect similar attacks based on NetCAT in the future," the paper reads. We hope that our efforts caution processor vendors against exposing microarchitectural elements to peripherals without a thorough security design to prevent abuse." The team also published a video briefing the nature of NetCAT. AMD EPYC processors don't support DDIO.The video detailing NetCAT follows.