Intel is preparing lots of interesting designs for the future and it is slowly shaping their vision for the next generation of computing devices. Following the big.LITTLE design principle of Arm, Intel decided to try and build its version using x86-64 cores instead of Arm ones, called Lakefield. And we already have some information about the new Alder Lake CPUs based on Lakefield design that are set to be released in the future. Thanks to a report from Chrome Unboxed, who found the patches submitted to Chromium open-source browser, used as a base for many browsers like Google Chrome and new Microsoft Edge, there is a piece of potential information that suggests Alder Lake CPUs could arrive very soon.

Rumored to feature up to 16 cores, Alder Lake CPUs could present an x86 iteration of the big.LITTLE design, where one pairs eight "big" and eight "small" cores that are activated according to increased or decreased performance requirements, thus bringing the best of both worlds - power efficiency and performance. This design would be present on Intel's 3D packaging technology called Foveros. The Alder Lake CPU support patch was added on April 27th to the Chrome OS repository, which would indicate that Intel will be pushing these CPUs out relatively quickly. The commit message titled "add support for ADL gpiochip" contained the following: "On Alderlake platform, the pinctrl (gpiochip) driver label is "INTC105x:00", hence declare it properly." The Chrome Unboxed speculates that Alder Lake could come out in mid or late 2021, depending on how fast Intel could supply OEMs with enough volume.

Apple is currently designing a custom series of CPUs, for its Macbook laptop lineup, based on the Arm Instruction Set Architecture. Having designed some of the most powerful mobile processors that are inside the iPhone series of devices, Apple is preparing to make a jump to an even more powerful device lineup by bringing custom CPUs for MacBook. Tired of the speed by which Intel replaces and upgrades its Core lineup of CPUs, Apple decided to take the matter in its own hands and rumors about the switch to a custom solution have been going on for a while. However, we now have some information about when to expect the first wave of Arm-powered Macs.

According to the analyst Ming-Chi Kuo, who is a well-known insider in the Apple industry, we can expect the first wave of the Arm-powered Macbook in the next 18 months, precisely in the first half of 2021. Supposedly, the first chips for these new Macs are going to be manufactured on a 5 nm manufacturing process, possibly over at TSMC since Apple had a long-lasting history of manufacturing its chips at TSMC foundries. In the meantime, we can expect to see Apple providing developers with tools to transition their x86-64 software to the new Arm ISA. Without a software ecosystem, the hardware platform is essentially worthless. And Apple knows this. We will see how they plan to play it and will report as soon as there is more information.

VIA's CenTaur division sprung an unexpected surprise in the CPU industry with its new CHA x86-64 microarchitecture and an on-die NCORE AI co-processor. This would be the first globally-targeted x86 processor launch by a company other than Intel and AMD in close to 7 years, and VIA's first socketed processor in over 15 years. SemiAccurate scored a look at mock-up of the CenTaur CHA NCORE 8-core processor and it turns out that the chip is indeed socketed.

Pictured below, the processor is a flip-chip LGA. We deduce it is socketed looking at its alignment notches and traces for ancillaries on the reverse-side (something BGAs tend to lack). On the other hand, the "contact points" of the package appear to cast shadows, and resemble balls on a BGA package. Topside, we see an integrated heatspreader (IHS), and underneath is a single square die. CenTaur built the CHA NCORE on TSMC's 16 nm FinFET process. The package appears to have quite a high pin-count for a die this size, but that's probably because of its HEDT-rivaling I/O, which includes a quad-channel DDR4 memory interface and 44 PCI-Express gen 3.0 lanes.

Microsoft is determined in its goal to move away from x86-64 dominance it had in the personal computer space for many decades. In the latest Windows 10 Insider Preview Build 19559, Microsoft has enabled Hyper-V support for ARM64 devices, such as Surface Pro X. Hyper-V is a Windows native hypervisor and it is Microsoft's virtualization technology that allows running other OSes on top of Windows. Being a low-overhead solution, it is more efficient than a virtual machine and allows for better performance of OS that is running on top of Windows.

With the Insider Preview Build 19559, Microsoft is enabling this feature on a Windows 10 Pro and Windows 10 Enterprise customers. It is important to note that by adding more features like this, Microsoft is expanding the software ecosystem of ARM64 devices, which should result in wider adoption of PCs like the Surface Pro X.

Market intelligence firm Mercury Research published its findings on the x86 processor market towards the end of 2019, in which AMD has posted growth in all segments (not counting IoT or semi-custom). AMD held 18.3 percent of the desktop x86 processor market, according to the report. a 5-year high. The company's EPYC line of server processors face a more uphill battle against enterprises' entrenched brand loyalties to Intel. The company holds 4.5 percent of the server processor market, but growing 0.2 percent points versus the previous quarter, and 1.4 percentage points vs. the previous year. The last time AMD held such a market share in the server x86 processor market was in Q3-2013.

AMD's mobile processor market share may come as a surprise to some. According to Mercury Research, the company holds 16.2 percent of the mobile x86 processor market, which is almost as much as its desktop market. This is probably propelled by the popularity of AMD APUs and low-power CPUs in the cost-effective notebook market segments. AMD is now eyeing higher market segments with its Ryzen 4000 "Renoir" processors that make landfall this year. AMD is growing faster in the mobile space than desktop, with 1.5 percentage points growth in just Q4, and 4 percentage points year-over-year. AMD's mobile market share was this high back in Q2-2013. Mercury Research pins AMD's overall hold over the x86 market at 15.5%, averaged on all segments, minus semi-custom and IoT.

Zhaoxin is a brand that makes multi-core 64-bit x86 processors primarily for use in Chinese state IT infrastructure. It's part of the Chinese Government's ambitious plan to make its IT hardware completely indigenous. Zhaoxin's x86-64 CPU cores are co-developed by licensee VIA, specifically its CenTaur subsidiary that's making NCORE AI-enabled x86 processors. The company's KaiXian KX-6780A processor is now commercially available in China to the DIY market in the form of motherboards with embedded processors.

The KaiXian KX-6780A features an 8-core/8-thread x86-64 CPU clocked up to 2.70 GHz, 8 MB of last-level cache, a dual-channel DDR4-3200 integrated memory controller, a PCI-Express gen 3.0 root-complex, and an iGPU possibly designed by VIA's S3 Graphics division, which supports basic display and DirectX 11.1 readiness. The CPU features modern ISA, with instruction sets that include AVX, AES-NI, SHA-NI, and VT-x comparable virtualization extensions. The chip has been fabricated on TSMC 16 nm FinFET process.

Intel Core i5-L16G7 is the first commercial SKU that implements Intel's "Lakefield" heterogenous x86 processor architecture. This 5-core chip features one high-performance "Sunny Cove" CPU core, and four smaller "Tremont" low-power cores, with an intelligent scheduler balancing workloads between the two core types. This is essentially similar to ARM big.LITTLE. The idea being that the device idles most of the time, when lower-powered CPU cores can hold the fort; performance cores kick in only when really needed, until which time they remain power-gated. Thai PC enthusiast TUM_APISAK discovered the first public appearance of the i5-L16G7 in an unreleased Samsung device that has the Userbenchmark device ID string "SAMSUNG_NP_767XCL."

Clock speeds of the processor are listed as "1.40 GHz base, with 1.75 GHz turbo," but it's possible that the two core types have different clock-speed bands, just like the cores on big.LITTLE SoCs. Other key components of "Lakefield" include an iGPU based on the Gen11 graphics architecture, and an LPDDR4X memory controller. "Lakefield" implements Foveros packaging, in which high-density component dies based on newer silicon fabrication nodes are integrated with silicon interposers based on older fabrication processes, which facilitate microscopic high-density wiring between the dies. In case of "Lakefield," the Foveros package features a 10 nm "compute field" die sitting atop a 22 nm "base field" interposer.

Tasting Intel's blood in the water with AMD's return to competitiveness, dormant x86 licensee VIA wants to take another swing at the market, this time with a multi-core processor targeted at enterprises and possibly workstations, developed by its subsidiary CenTaur. The company appears to want to cash in on the AI boom, and could develop turnkey facial-recognition CCTV solutions with the chip. CenTaur is ready with a working prototype. It features eight 64-bit x86 CPU cores, and an on-die "AI co-processor" named NCORE. A ringbus connects the eight CPU cores and the NCORE with the processor's other components. The processor features 16 MB of shared L3 cache, a quad-channel DDR4-3200 memory interface, and a 44-lane PCI-Express gen 3.0 root-complex, along with a fully integrated southbridge, making it an SoC. It also appears to be multi-socket capable, although VIA didn't detail the interconnect in use.

The NCORE is a PCI-mapped device to the software, which provides functions such as DNN building and training acceleration. From the looks of it, there's more to NCORE than simply a fixed-function hardware that multiplies matrices. Its developers state that the device accelerates AI at a rate of "20 trillion AI operations/sec with 20 terabytes/sec memory bandwidth." The CPU cores on the processor tick at 2.50 GHz, and while VIA hasn't made any IPC claims, it has mentioned support for the cutting-edge AVX-512 instruction-set, something even "Zen 2" lacks, which possibly indicates a powerful FPU. The silicon measures 195 mm², and has been built on 16 nm FinFET node at TSMC. VIA will demonstrate the unnamed processor and its testbed at ISC East 2019, held on November 20 and 21.The full technology announcement slide-deck follows.

At Supercomputing 2019, Intel unveiled its vision for extending its leadership in the convergence of high-performance computing (HPC) and artificial intelligence (AI) with new additions to its data-centric silicon portfolio and an ambitious new software initiative that represents a paradigm shift from today's single-architecture, single-vendor programming models.

Addressing the increasing use of heterogeneous architectures in high-performance computing, Intel expanded on its existing technology portfolio to move, store and process data more effectively by announcing a new category of discrete general-purpose GPUs optimized for AI and HPC convergence. Intel also launched the oneAPI industry initiative to deliver a unified and simplified programming model for application development across heterogenous processing architectures, including CPUs, GPUs, FPGAs and other accelerators. The launch of oneAPI represents millions of Intel engineering hours in software development and marks a game-changing evolution from today's limiting, proprietary programming approaches to an open standards-based model for cross-architecture developer engagement and innovation.

According to the sources close to Neowin, Microsoft is expected to launch x86-64 (or x64 in short) emulation support for Windows on ARM (WoA) devices. Expected to arrive in Windows 10 21H1, or around 2020 for all the Windows Insiders, the new feature will enable a vast majority of apps made for Windows OS, currently built for x64 architecture, to run on ARM ISA and all Windows on ARM computers.

So far, only 32-bit x86 applications were able to be emulated, however, if these rumors are to be believed, many users of WoA devices should get a chance to run all of their favorite 64-bit software that was previously unavailable. The launch of this feature will boost the adoption of the WoA ecosystem with benefits reaching all existing laptop models, including Microsoft's newly launched Surface Pro X laptop that utilizes an ARM-based chip called SQ1 (customized Qualcomm Snapdragon 8cx processor).

G.SKILL, the world's leading manufacturer of extreme performance memory and gaming peripherals, is very thrilled to announce a new world record for the fastest memory frequency at DDR4-6016.8 MHz, being the first ever to break through the DDR4-6000 barrier. This milestone is set by the Taiwanese professional overclocker, TopPC, using G.SKILL DDR4 Trident Z Royal memory on the latest MSI MPG Z390I GAMING EDGE AC motherboard and Intel Core i9-9900K processor.

Just 3 short months after the world record DDR4-5886MHz set by Toppc at the G.SKILL Computex booth in June, Toppc has once again set a new world record for memory frequency speed and is the first to push DDR4 memory to an astonishing 6 GHz. The validation links for this major milestone can be found in the following CPU-Z validation link and HWBot website screenshot below (validation).

AMD in its 2nd generation EPYC processor launch event announced that it has completed the design phase of its next-generation "Zen 3" CPU microarchitecture, and is currently working on its successor, the "Zen 4." AMD debuted its "Zen 2" microarchitecture with the client-segment 3rd generation Ryzen desktop processor family, it made its enterprise debut with the 2nd generation EPYC. This is the first x86 CPU microarchitecture designed for the 7 nanometer silicon fabrication process, and is being built on a 7 nm DUV (deep ultraviolet) node at TSMC. It brings about double-digit percentage IPC improvements over "Zen+."

The "Zen 3" microarchitecture is designed for the next big process technology change within 7 nm, EUV (extreme ultraviolet), which allows significant increases in transistor densities, and could facilitate big improvements in energy-efficiency that could be leveraged to increase clock-speeds and performance. It could also feature new ISA instruction-sets. With "Zen 3" passing design phase, AMD will work on prototyping and testing it. The first "Zen 3" products could debut in 2020. "Zen 4" is being designed for a different era.

Intel today announced its future Intel Xeon Scalable processor family (codename Cooper Lake) will offer customers up to 56 processor cores per socket and built-in AI training acceleration in a standard, socketed CPU as part of its mainline Intel Xeon Scalable platforms, with availability in the first half of 2020. The breakthrough platform performance delivered within the high-core-count Cooper Lake processors will leverage the capabilities built into the Intel Xeon Platinum 9200 series, which today is gaining momentum among the world's most demanding HPC customers, including HLRN, Advania, 4Paradigm, and others.

"The Intel Xeon Platinum 9200 series that we introduced as part of our 2nd Generation Intel Xeon Scalable processor family generated a lot of excitement among our customers who are deploying the technology to run their high-performance computing (HPC), advanced analytics, artificial intelligence and high-density infrastructure. Extended 56-core processor offerings into our mainline Intel Xeon Scalable platforms enables us to serve a much broader range of customers who hunger for more processor performance and memory bandwidth."
-Lisa Spelman, vice president and general manager of Data Center Marketing, Intel Corporation

During its second quarter earnings call, Intel announced that it has started shipping of 10th generation "Core" CPUs to OEMs. Making use of 10 nm lithography, the 10th generation of "Core" CPUs, codenamed Ice Lake, were qualified by OEMs earlier in 2019 in order to be integrated into future products. Ice Lake is on track for holiday season 2019, meaning that we can expect products on-shelves by the end of this year. That is exciting news as the 10th generation of Core CPUs is bringing some exciting micro-architectural improvements along with the long awaited and delayed Intel's 10nm manufacturing process node.

The new CPUs are supposed to get around 18% IPC improvement on average when looking at direct comparison to previous generation of Intel CPUs, while being clocked at same frequency. This time, even regular mobile/desktop parts will get AVX512 support, alongside VNNI and Cryptography ISA extensions that are supposed to bring additional security and performance for the ever increasing number of tasks, especially new ones like Neural Network processing. Core configurations will be ranging from dual core i3 to quad core i7, where we will see total of 11 models available.

AMD Lisa Su at Computex 2019 confirmed to Tom's hardware that the company wasn't licensing anymore of its x86 IP portfolio to China-based companies. AMD entered a technology license agreement with China's Tianjin Haiguang Advanced Technology Investment Co. Ltd. (THATIC) in 2016. As part of the agreement to license its x86 and SoC IP for chip development, AMD received a cash infusion worth $293 million (plus royalties).

As a result, Chinese chipmaker Hygon started delivering their "Dhyana" CPUs, which looked like copies of AMD's Zen-based Epyc chips with added, Chinese-government approved cryptographic capabilities. AMD had to go through some hoops to get this deal done, but it did. However, now the technology refinement pipe is draining for the Chinese companies, as AMD won't be delivering its post-Zen updates to the core design. It remains to be seen if AMD's intellectual property was enough for Chinese companies to ignite their own in-country CPU development, or if the ongoing US-China trade war will keep on draining the company of CPU independence.

Today Intel announced ModernFW - an experimental approach to building a minimum viable platform firmware for machines such as cloud server platforms. The reason for this software is that, while traditional PC Firmware has evolved over time and retained its backward compatibility, it has become very big and often inefficient.

So to meet the requirements of new platforms that need to be built quickly and adapted easily, Intel decided to offer a new software package that will help with that. The new firmware package targets x86_64 from ISA standpoint and Linux kernel based OSes.

Intel has unceremoniously, through a product change notification (PCN), discontinued the Itanium family of microprocessors. The Itanium 9700 "Kittson," which was released in 2017, is the final generation of Itanium, and its sales to new customers have stopped according to the PCN. The series has been marked "end of life" (EOL). Existing customers of Itanium who already have their IT infrastructure built around Itanium 9700 series, have an opportunity to determine their remaining demand of these processors, and place their "Last Product Discontinuance" order with Intel. The final LPD shipments would go out mid-2021.

With this move, Intel has cast uncertainty over the future of the IA-64 microarchitecture. IA-64 was originally conceived by Intel to replace 32-bit x86 at the turn of the century, as an industry-standard 64-bit processor architecture. AMD laid the foundation for its rival standard AMD64, which could go on to become x86-64. AMD64 won the battle for popularity over IA-64, as it maintained complete backwards-compatibility with x86, and could seamlessly run 32-bit software, saving enterprises and clients billions in transition costs. Intel cross-licensed it as EM64T (extended memory 64-bit technology), before standardizing the name x86-64. Itanium dragged on for close to two decades serving certain enterprise and HPC customers.

Intel today unveiled a killer new product with which it hopes to bring about as big a change to mobile computing as Ultrabook did some eight years ago. This effort is a combination of a new mobile computing form-factor codenamed "Project Athena," and an SoC at its heart, codenamed "Lakefield." Put simply, "Lakefield" is a 10 nm SoC that's integrated much in the same way as today's ARM SoCs, which combine IP from various vendors onto a single PoP (package-over-package) Foveros die.

The biggest innovation with "Lakefield" is its hybrid x86 multi-core CPU design, which combines four Atom-class low-power cores, with one Core-class "Sunny Cove" core, in a setup akin to ARM's big.LITTLE. Low-power processing loads are distributed to the smaller cores, while the big core is woken up to deal with heavy loads. The SoC also integrates a Gen 11 iGPU core, partial components to accelerate 802.11ax WLAN, 5G, an PoP DRAM and NVMe storage devices. The reference motherboard based on "Lakefield" is barely larger than an M.2 SSD!

Intel at its architecture day revealed one of the more exquisite in-house designs for the company in recent years: a hybrid x86 chip that seems to imbibe from ARM's own big.Little design mantra. The new Hybrid x86 CPU that was announced takes this design choice in pairing a single, high-performance Sunny Cove core with four smaller Atom cores. This chip is built using Intel's Foveros manufacturing technology, which means a 22FFL IO chip serves as an active interposer, connected via TSVs to a 10nm die that contains both types of cores. The tiny chips measures just 12 x 12 x 1 mm (144 mm²), and looks to reduce footprint even further by including a POP (package on package) memory design.

The new Intel design is aimed at low-power environments, with the chip having been designed to work on a 2 mW standby power ratio, with less than a 7 W of power - for a big.Little five-core design and a 64 EU design with Gen11 graphics core. Intel's Jim Keller said that the company is testing the intricacies and advantages of this design internally, so more products based on this manufacturing and packaging mantra could pop up sometime in the future.

AMD recently announced the Radeon Instinct MI60, a GPU-based data-center compute processor with hardware virtualization features. It takes the crown for "the world's first 7 nm GPU." The company also put out specifications of the "Vega 20" GPU it's based on: 4,096 stream processors, 4096-bit HBM2 memory interface, 1800 MHz engine clock-speed, 1 TB/s memory bandwidth, 7.4 TFLOP/s peak double-precision (FP64) performance, and the works. Here's the kicker: the company isn't launching this accelerator with Windows support. At launch, AMD is only releasing x86-64 Linux drivers, with API support for OpenGL 4.6, Vulkan 1.0, and OpenCL 2.0, along with AMD's ROCm open ecosystem. The lack of display connector already disqualifies this card for most workstation applications, but with the lack of Windows support, it is also the most expensive graphics card that "can't run Crysis." AMD could release Radeon Pro branded graphics cards based on "Vega 20," which will ship with Windows and MacOS drivers.

Today at Oracle OpenWorld 2018, AMD (NASDAQ: AMD) announced the availability of the first AMD EPYCTM processor-based instance on Oracle Cloud Infrastructure. With this announcement, Oracle becomes the largest public cloud provider to have a Bare Metal version on AMD EPYCTM processors1. The AMD EPYC processor-based "E" series will lead with the bare metal, Standard "E2", available immediately as the first instance type within the Series. At $0.03/Core hour, the AMD EPYC instance is up to 66 percent less on average per core than general purpose instances offered by the competition2 and is the most cost-effective instance available on any public cloud.

"With the launch of the AMD instance, Oracle has once again demonstrated that we are focused on getting the best value and performance to our customers," said Clay Magouyrk, senior vice president, software development, Oracle Cloud Infrastructure. "At greater than 269 GB/Sec, the AMD EPYC platform3, offers the highest memory bandwidth of any public cloud instance. Combined with increased performance, these cost advantages help customers maximize their IT dollars as they make the move to the cloud."

Intel has submitted the first patches with Vulkan support to their open-source OpenCV library, which is designed to accelerate Computer Vision. The library is widely used for real-time applications as it comes with 1st-class optimizations for Intel processors and multi-core x86 in general. With Vulkan support, existing users can immediately move their neural network workloads to the GPU compute space without having to rewrite their code base.

At this point in time, the Vulkan backend supports Convolution, Concat, ReLU, LRN, PriorBox, Softmax, MaxPooling, AvePooling, and Permute. According to the source code changes, this is just "a beginning work for Vulkan in OpenCV DNN, more layer types will be supported and performance tuning is on the way."

It seems that now, with their own GPU development underway, Intel has found new love for the GPU-accelerated compute space. The choice of Vulkan is also interesting as the API is available on a wide range of platforms, which could mean that Intel is trying to turn Vulkan into a CUDA killer. Of course there's still a lot of work needed to achieve that goal, since NVIDIA has had almost a decade of head start.

VIA processors probably make up an infinitesimal amount of the desktop PC market-share, and its makers market the chip only at pre-built machines such as digital-signage kiosks, information kiosks, ticket vending machines, ATMs, etc (which don't need a lot of processing power). At the Black Hat 2018 conference, security researcher Christopher Domas discovered that getting access to root privileges in Linux on a machine powered by VIA C3 "Nehemiah" processors is laughably easy. Just key in ".byte 0x0f, 0x3f" (without quotes) in any Linux CLI in user mode, and voila! You are now the root user.

Domas calls this his own iddqd (the cheat-code for "God Mode" in "Doom"). This backdoor, probably put in place by the processor's designers themselves, completely collapses the ring-based privilege system of the operating system, and elevates users and applications from the ring-2 (and above) userspace to ring 0 (root). It is an exploitation of a shadow-core, a hidden RISC processor within C7, which manages the startup, operation, and key storage of the x86 cores. Intel and AMD too have shadow-cores with similar functions.

Intel's Xeon Phi lineup, which started as Larrabee. has never seen any commercial success in the market despite big promises from the big blue giant that its programming model would be more productive for developers coming from x86. In the meantime, NVIDIA GPUs have taken over the world of supercomputing, with the latest generation Volta decimating Intel Xeon Phi offerings.

Intel's plan was to release a new generation of Xeon Phi called "Knights Hill", on a 10 nanometer process. However, constant delays ramping up 10 nm, paired with generally low demand for Xeon Phi, forced the company to abandon this project. Now the company announces that they are stopping production for eight currently shipping Xeon Phi models.

Chinese chipmaker Hygon began mass-producing its first x86 processors codenamed "Dhyana" based on AMD's "Zen" micro-architecture. The processor is the fruition of a deal AMD entered with a Chinese state-owned company back in mid-2016. As part of this deal, a company called Haiguang Microelectronics Company (HMC), in which AMD has a 51 percent stake, would license the "Zen" architecture to another company called Hygon (Chengdu Haiguang Integrated Circuit Design Co.), in which AMD owns a 30 percent stake. Hygon would then design "Dhyana," and a third entity (likely TSMC or some other Chinese foundry), would contract-manufacture the chip.

Such legal gymnastics is necessary to ensure AMD makes good on the $293 million it will take from the Chinese firms to license "Zen," while not breaching the x86 architecture cross-licensing agreement it signed with Intel, the core x86 IP owner. Chinese firms are going through all this trouble to build "Dhyana" instead of simply placing a large order of EPYC processors not just because they want more control over the supply and pricing of these chips, but probably also to ensure that China can keep an eye on all the on-die software that makes the processor tick, and weed out any backdoors to foreign governments (*cough*NSA*cough*).