Friday, February 5th 2021
Microchip Announces World's First PCI Express 5.0 Switches
Applications such as data analytics, autonomous-driving and medical diagnostics are driving extraordinary demands for machine learning and hyperscale compute infrastructure. To meet these demands, Microchip Technology Inc. today announced the world's first PCI Express (PCIe) 5.0 switch solutions—the Switchtec PFX PCIe 5.0 family—doubling the interconnect performance for dense compute, high speed networking and NVM Express (NVMe ) storage. Together with the XpressConnect retimers, Microchip is the industry's only supplier of both PCIe Gen 5 switches and PCIe Gen 5 retimer products, delivering a complete portfolio of PCIe Gen 5 infrastructure solutions with proven interoperability.
"Accelerators, graphic processing units (GPUs), central processing units (CPUs) and high-speed network adapters continue to drive the need for higher performance PCIe infrastructure. Microchip's introduction of the world's first PCIe 5.0 switch doubles the PCIe Gen 4 interconnect link rates to 32 GT/s to support the most demanding next-generation machine learning platforms," said Andrew Dieckmann, associate vice president of marketing and applications engineering for Microchip's data center solutions business unit. "Coupled with our XpressConnect family of PCIe 5.0 and Compute Express Link (CXL ) 1.1/2.0 retimers, Microchip offers the industry's broadest portfolio of PCIe Gen 5 infrastructure solutions with the lowest latency and end-to-end interoperability."
The Switchtec PFX PCIe 5.0 switch family comprises high density, high reliability switches supporting 28 lanes to 100 lanes and up to 48 non-transparent bridges (NTBs). The Switchtec technology devices support high reliability capabilities, including hot-and surprise-plug as well as secure boot authentication. With PCIe 5.0 data rates of 32 GT/s, signal integrity and complex system topologies pose significant development and debug challenges. To accelerate time-to-market, the Switchtec PFX PCIe 5.0 switch provides a comprehensive suite of debug and diagnostic features including sophisticated internal PCIe analyzers supporting Transaction Layer Packet (TLP) generation and analysis and on-chip non-obtrusive SerDes eye capture capabilities. Rapid system bring-up and debug is further supported with ChipLink—an intuitive graphical user interface (GUI) based device configuration and topology viewer that provides full access to the PFX PCIe switch's registers, counters, diagnostics and forensic capture capabilities.
"Intel's upcoming Sapphire Rapids Xeon processors will implement PCI Express 5.0 and Compute Express Link running up to 32.0 GT/s to deliver the low-latency and high-bandwidth I/O solutions our customers need to deploy," said Dr. Debendra Das Sharma, Intel fellow and director of I/O technology and standards. "We are pleased to see Microchip's PCIe 5.0 switch and retimer investment strengthen the ecosystem and drive broader deployment of PCIe 5.0 and CXL enabled solutions."
Development Tools
Microchip has released a full set of design-in collateral, reference designs, evaluation boards and tools to support customers building systems that take advantage of the high-bandwidth of PCIe 5.0.
In addition to PCIe technology, Microchip also provides data center infrastructure builders worldwide with total system solutions including RAID over NVMe, storage, memory, timing and synchronization systems, stand-alone secure boot, secure firmware and authentication, wireless products, touch-enabled displays to configure and monitor data center equipment and predictive fan controls.
Availability
The Switchtec PFX PCIe 5.0 family of switches are sampling now to qualified customers. For additional information, contact a Microchip sales representative.
"Accelerators, graphic processing units (GPUs), central processing units (CPUs) and high-speed network adapters continue to drive the need for higher performance PCIe infrastructure. Microchip's introduction of the world's first PCIe 5.0 switch doubles the PCIe Gen 4 interconnect link rates to 32 GT/s to support the most demanding next-generation machine learning platforms," said Andrew Dieckmann, associate vice president of marketing and applications engineering for Microchip's data center solutions business unit. "Coupled with our XpressConnect family of PCIe 5.0 and Compute Express Link (CXL ) 1.1/2.0 retimers, Microchip offers the industry's broadest portfolio of PCIe Gen 5 infrastructure solutions with the lowest latency and end-to-end interoperability."
"Intel's upcoming Sapphire Rapids Xeon processors will implement PCI Express 5.0 and Compute Express Link running up to 32.0 GT/s to deliver the low-latency and high-bandwidth I/O solutions our customers need to deploy," said Dr. Debendra Das Sharma, Intel fellow and director of I/O technology and standards. "We are pleased to see Microchip's PCIe 5.0 switch and retimer investment strengthen the ecosystem and drive broader deployment of PCIe 5.0 and CXL enabled solutions."
Development Tools
Microchip has released a full set of design-in collateral, reference designs, evaluation boards and tools to support customers building systems that take advantage of the high-bandwidth of PCIe 5.0.
In addition to PCIe technology, Microchip also provides data center infrastructure builders worldwide with total system solutions including RAID over NVMe, storage, memory, timing and synchronization systems, stand-alone secure boot, secure firmware and authentication, wireless products, touch-enabled displays to configure and monitor data center equipment and predictive fan controls.
Availability
The Switchtec PFX PCIe 5.0 family of switches are sampling now to qualified customers. For additional information, contact a Microchip sales representative.
9 Comments on Microchip Announces World's First PCI Express 5.0 Switches
That said, I wonder if PCIe 5.0 will be the mainstream for years to come; while everything else catches up (storage, GPUs, etc), or if AMD and Intel will continue to push the latest PCIe once it matures enough (IIRC, PCIe 6.0 is already close to being finalized, if not already). Only reason I'd suspect both pushing beyond is due to all the bandwidth and speeds needed by ultra-specialized accelerators, which use their own special interconnects. But that's normally a commercial feature. Then again, with their chiplet manufacturing, it likely wouldn't cost too much to adapt the I/O die to the consumer market, and keep playing the "I have it while the competition doesn't". The only real cost then would be the repeaters needed on the mobos.
Bring it...
like, yesterday, hehehe :roll:
Most consumer systems need - if anything - more lanes. Unless the speed is used to drop the number of lanes to a GPU to x8 without a performance penalty, which would mean 8 more lanes for other devices. I don't see that happening though cause, you know, marketing.
Undoubtedly, we need more modern and more productive technologies, at least to reduce the prices of currently available hardware, or to push it to the second-hand market, where it is even cheaper. Remember how expensive the 9900K was when it first hit the market, now even in my country, with the big markups on retailers, this processor sells for around €400. This is price for new CPU in the box and full warranty for the end customers and include 20% VAT. Was €650-700 for first.
So you get ~40-lanes of PCIe 4.0 (or ~20-lanes of PCIe 5.0) before you literally run out of DDR4 / DDR5 bandwidth.
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A PCIe switch means that those 16 lanes can go to different devices. Maybe you have 16-lanes to GPU#1, and then the same 16-lanes to your 4x RAID0 NVMe array. Your CPU / DDR4 is only built for 32GBps to the 16x lane PCIe4 (or maybe 64GBps PCIe 5.0 x16), because a switch can only talk to one-or-the-other at a time (not both simultaneously). So... I think a switch accomplishes what you're asking.
For most people, increasing the number of lanes results in the ability to add more M.2 storage and use it at its full potential. For example, I have 6 SATA ports, but only two M.2 slots.
I would really prefer to have four full speed M.2 slots, or even six, but very few boards have more than 2 due to the low number of PCIe lanes. I don't necessarily want to 'junk' say a 512GB M.2 just because I bought a 1 or 2 TB one, same logic as for sata ports which is why there are so many, but ultimately I'll be faced with that choice.
Anyway, I don't think we'll see more lanes anytime real soon outside of HEDT, which really has enough lanes already I suspect as time goes on desktop systems become less influential, laptops more influential, and laptops don't need more lanes. Hence, unlikely anyone will bother adding more lanes to regular consumer CPUs / chipsets.