Saturday, July 20th 2024

Intel Intros 14th Gen Core "E" Embedded Processors with E-cores Disabled

by
btarunr
 Discuss (64 Comments)
Intel introduced a line of 14th Gen Core "Raptor Lake Refresh" Socket LGA1700 processors for the embedded systems market. A highlight of these chips is that they come with their "Gracemont" E-core clusters disabled, and are pure P-core chips. It's interesting that Intel targets these chips for the embedded systems segment, but isn't building these in the non-socketed BGA packages carried over from its mobile platforms. Intel is addressing nearly all performance market-segments with these chips, including the very top. The Core i9-14901KE processor leading the pack is an 8-core/16-thread chip with eight "Raptor Cove" cores sharing the full 36 MB L3 cache available on the "Raptor Lake-S" die, a maximum boost frequency of 5.80 GHz, base frequency of 3.80 GHz, and processor base power of 125 W. The chip features an iGPU. The "K" in KE denotes that the chip supports overclocking.

Next up, is the Core i9-14901E, the 65 W sibling of this chip, which lacks an unlocked multiplier, and boosts up to 5.60 GHz, with a 2.80 GHz base frequency. Things get interesting with the Core i7-14701E, because the differentiator between the Core i9 and Core i7 SKUs is E-core count, and here we see the i7-14701 retaining the same 8-core/16-thread pure P-core configuration as the Core i9 chips, but with a touch lower frequencies of 5.40 GHz maximum boost, and 2.60 GHz base.
The Core i5-14501E is a 6-core/12-thread processor based on the larger "Raptor Lake-S" die, unlike the regular Core i5-14500 that uses the "Alder Lake-S" die. The 6 P-cores share 24 MB of L3 cache, and each feature 2 MB of dedicated L2 cache, unlike the i5-14500, which sees 1.25 MB of L2 cache per P-core, besides the 8 E-cores. This chip boosts up to 5.20 GHz, and has a base frequency of 3.30 GHz. The i5-14501TE is a variant of this chip with 45 W processor base power, 5.10 GHz maximum boost frequency, and 2.20 GHz base frequency.

Lastly, there are the Core i5-14401E, i5-14401EF, and the i5-14401TE. The first two are differentiated with the i5-14401EF lacking integrated graphics, the first two are 65 W chips, while the i5-14401TE is 45 W. The i5-14401E/EF boost up to 4.70 GHz, with a 2.50 GHz base frequency, while the i5-14401TE boosts up to 4.50 GHz, with a 2.00 GHz base frequency.

All chips in the 14th Gen Core E-series feature the same I/O as the regular 14th Gen Core desktop processors, with a PCI-Express 5.0 x16 PEG interface, a CPU-attached Gen 4 x4 NVMe interface, and a DMI 4.0 x8 chipset bus. The memory interface supports dual-channel DDR4 and DDR5 memory types.
Sources: VideoCardz, Jaykihn (Twitter)

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64 Comments on Intel Intros 14th Gen Core "E" Embedded Processors with E-cores Disabled

#51
ratirt
Can you guys say with 100% certainty, that the ecore are broken or malfunctioning thus being cut out or Intel's decision was not to use them even though they are OK?
I did not see the article say these are broken or defective. Maybe, these are not defective and the reason Intel disables the cluster is different than the obvious one 'defective cores'.
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#52
AusWolf
ratirtCan you guys say with 100% certainty, that the ecore are broken or malfunctioning thus being cut out or Intel's decision was not to use them even though they are OK?
I did not see the article say these are broken or defective. Maybe, these are not defective and the reason Intel disables the cluster is different than the obvious one 'defective cores'.
That's equally possible. That's why I wrote "speculation" in brackets. Until Intel does an official announcement, or someone does a thorough investigation, we won't know for sure.
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#53
joemama
Why would Intel intentionally turn off some cores to sell their product with a lower price? Only reviving defective chips would make sense
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#54
watzupken
AusWolfUnless it's a silent admission that the problem is with the e-cores, and they just want to keep selling something instead of doing a recall. (speculation)
I am not too sure about it. The ability to disable E-cores is already available. So it is not difficult for reviewers or investigators to find out the issue. Regardless, if Intel is not confirming the issue, all the more people should avoid anything to do with Raptor Lake.
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#55
Dr. Dro
CrackongAre these fused off silicon ? or the E-core spaces just empty ?
Fused off.
atomsymbolSilicon that is disabled, but is nevertheless present on the chip and is otherwise fully functional, is a waste of natural resources and a waste of chip manufacturing capacity.
Quite contrary. Chip harvesting allows imperfect processor dies to be sold as otherwise fully functioning processors. If you own a Core i7 or i5, or a Ryzen 5/Ryzen 9 x900 series, you have a harvest in your hands.
watzupkenI am not too sure about it. The ability to disable E-cores is already available. So it is not difficult for reviewers or investigators to find out the issue.
CPU manufacturing is a very complicated process, and imperfections can be present in any area of the processor. This one has the four e-core clusters and associated L2 cache disabled. What's interesting is that the full L3 slice is enabled on the 14901KE, which may mean that the L3 cache that is normally attribute to an e-core cluster is not necessarily an inherent part of it and can be accessed by the P-cores normally.
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#56
InVasMani
Dr. DroFused off.



Quite contrary. Chip harvesting allows imperfect processor dies to be sold as otherwise fully functioning processors. If you own a Core i7 or i5, or a Ryzen 5/Ryzen 9 x900 series, you have a harvest in your hands.



CPU manufacturing is a very complicated process, and imperfections can be present in any area of the processor. This one has the four e-core clusters and associated L2 cache disabled. What's interesting is that the full L3 slice is enabled on the 14901KE, which may mean that the L3 cache that is normally attribute to an e-core cluster is not necessarily an inherent part of it and can be accessed by the P-cores normally.
If you disable E-cores it negates a bunch of added strain off the Ring by extension because L3 cache is connected with Ring and accessible by the E-cores. I don't believe there is a bios to enable L3 cache access only to P cores or not that I know of on my Asus board at least. I wonder if they could even implement a bios option to limit a ratio of how much access to L3 E-cores can receive if it's creating problems in heavy MT scenario's. The only conclusions I have is these chips are really sensitive in terms of stability given how far they've been pushed and with how many cores they include. Plus there are other outside conditions complicating matters like MB makers defaults adding fuel to the fire.

I tried to dig for a few voltage spec settings in Intel's PDF of 13th/14th gen, but they didn't seem to provided it for L2 cache voltage and cache voltage. It would be nice to know what's minimum, typical, max on those yet I couldn't find those details and I tried.
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#57
kondamin
ratirtCan you guys say with 100% certainty, that the ecore are broken or malfunctioning thus being cut out or Intel's decision was not to use them even though they are OK?
I did not see the article say these are broken or defective. Maybe, these are not defective and the reason Intel disables the cluster is different than the obvious one 'defective cores'.
From all that I have been reading is that intel has pushed intel 7 to hard which is making the k parts rip them selves apart.

wouldnt surprise me one bit that if the p cores were disabled the chips that are crashing now would stop crashing as the e cores aren’t clocked to stupid speeds.
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#58
iameatingjam
kondaminFrom all that I have been reading is that intel has pushed intel 7 to hard which is making the k parts rip them selves apart.

wouldnt surprise me one bit that if the p cores were disabled the chips that are crashing now would stop crashing as the e cores aren’t clocked to stupid speeds.
ironically, it was the exact opposite for me, the only way I could make my 14700k boot was to disable at least 8 ecores. But thats one anecdotal case and we're hearing so much stuff right now its hard to know what is what.... the failures don't exactly follow a neat pattern. Which is why is we need some communication from intel. All we seem to know for sure is that higher clocks and higher voltages make it worse/speed it up, whatever the root problem is, maybe there's more than one root problem.
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#59
AusWolf
kondaminwouldnt surprise me one bit that if the p cores were disabled the chips that are crashing now would stop crashing as the e cores aren’t clocked to stupid speeds.
But they're a lot smaller (and maybe denser?) as well, so what doesn't seem like a stupidly high clock speed for p-cores could very well be one for e-cores.
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#60
Wirko
Dr. DroQuite contrary. Chip harvesting allows imperfect processor dies to be sold as otherwise fully functioning processors. If you own a Core i7 or i5, or a Ryzen 5/Ryzen 9 x900 series, you have a harvest in your hands.
Sure, but as the process matures, yields improve all the time. No one is willing to disclose any specific data, just some relative info like in this example graph (let's assume it's zero-based):



And then there are estimates by analysts such as TrendForce:
At present, the production yield rate of Sapphire Rapids is estimated at only 50~60%, which affects mainstream Sapphire Rapids MCC products. [November 2022]
which doesn't tell us the most basic thing - are the bad chips totally unusable, or do they just have a small number of bad cores out of 34?

2.5 years into Intel 7 manufacturing, I'd say it would be very bad for Intel if less than 50% of the CPUs on a Raptor Lake wafer were operative - I mean fully operative, with zero defects. They can't sell that many i9-13900/14900 chips (despite countless suffixes) because those all cost 440€ and up. So they still have to disable some good parts.
Dr. DroCPU manufacturing is a very complicated process, and imperfections can be present in any area of the processor. This one has the four e-core clusters and associated L2 cache disabled. What's interesting is that the full L3 slice is enabled on the 14901KE, which may mean that the L3 cache that is normally attribute to an e-core cluster is not necessarily an inherent part of it and can be accessed by the P-cores normally.
The same is true of the other chips in this new series, see my post #42. Interestingly, the two disabled P cores in the 14501E also have their L3 slices inoperative.
iameatingjamthe failures don't exactly follow a neat pattern. Which is why is we need some communication from intel. All we seem to know for sure is that higher clocks and higher voltages make it worse/speed it up, whatever the root problem is, maybe there's more than one root problem.
Exactly. I'd even suspect the power delivery system on the chip (and substrate too) first, which would mean that you can't pin the flaw to any of the cores.
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#61
atomsymbol
Dr. DroQuite contrary. Chip harvesting allows imperfect processor dies to be sold as otherwise fully functioning processors. If you own a Core i7 or i5, or a Ryzen 5/Ryzen 9 x900 series, you have a harvest in your hands.
It is extremely unlikely for chip manufacturing defects governed by laws of physics and chemistry to perfectly match (1) AMD/Intel's market segmentation, (2) market demand or (3) distribution of wealth in a society. ---- I mean it in the following sense: If AMD/Intel were serious about conserving Earth's resources and were selling what was manufactured, then for example Intel would be selling a CPU configuration like 5*Pcore + 1*Ecore and AMD would be selling 7*Zen4 CPUs.
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#62
Dr. Dro
atomsymbolIt is extremely unlikely for chip manufacturing defects governed by laws of physics and chemistry to perfectly match (1) AMD/Intel's market segmentation, (2) market demand or (3) distribution of wealth in a society. ---- I mean it in the following sense: If AMD/Intel were serious about conserving Earth's resources and were selling what was manufactured, then for example Intel would be selling a CPU configuration like 5*Pcore + 1*Ecore and AMD would be selling 7*Zen4 CPUs.
I agree but once you account for the sheer volume and intended market channels, it lines up. If demand exceeds supply by a significant margin then they will intentionally cap better CPUs to meet spec.
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#63
atomsymbol
Dr. DroIf demand exceeds supply by a significant margin then they will intentionally cap better CPUs to meet spec.
It is a valid approach. However, there exist alternative approaches.

It is fairly simple in a market economy to correct a demand-exceeds-supply disequilibrium: gradually increase prices in order for demand to match manufacturing capacity.

The other way around: When supply-exceeds-demand, gradually lower prices in order for demand to match manufacturing capacity.

If prices aren't increased/decreased gradually (that is: are increased/decreased sharply) it creates a very high risk of unhealthy oscillations in the economy. For example, search for "prey predator model dampening" in Google Images.
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#64
Evrsr
R0H1TNo what you're talking about is OoO not just SMT ~ to disable all possible side channel attacks you'd have to go back to the stone ages!
No OoO exec you can manage, as it is easier to stop speculation for which there is no privilege to access the data. This has already been implemented and the other situations where you don't want speculation for secure processes (memory re-ordering), this can be disabled for those.

With SMT, you can't really run secure processes on shared core and it costs die space and increases complexity. The OS has to make sure to not schedule two processes on the same core, so it quickly looses usefulness. Stuff servers want to run become severely limited, like virtual machines, web servers, encryption, etc.

OoO is also subject to this to some extent but the performance is worth the trouble, as it increases 3, 4 or 5x. I will say the future is looking like multithreading be powered by secure and isolated efficient cores. This is already mostly the case for Intel and ARM.
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