Wednesday, May 8th 2024
Core Configurations of Intel Core Ultra 200 "Arrow Lake-S" Desktop Processors Surface
Intel is giving its next-generation desktop processor lineup the Core Ultra 200 series processor model numbering. We detailed the processor numbering in our older report. The Core Ultra 200 series would be the company's first desktop processors with AI capabilities thanks to an integrated 50 TOPS-class NPU. At the heart of these processors is the "Arrow Lake" microarchitecture. Its development is the reason the company had to refresh "Raptor Lake" to cover its 2023-24 processor lineup. The company's "Meteor Lake" microarchitecture topped off at CPU core counts of 6P+8E, which would have proven to be a generational regression in multithreaded application performance over "Raptor Lake." The new "Arrow Lake-S" desktop processor has a maximum CPU core configuration of 8P+16E, which means consumers can expect at least the same core-counts at given price-points to carry over.
According to a report by Chinese tech publication Benchlife.info, the introduction of "Arrow Lake" would see Intel's desktop processor model numbering align with that of its mobile processor numbering, and incorporate the Core Ultra brand to denote the latest microarchitecture for a given processor generation. Since "Arrow Lake" is a generation ahead of "Meteor Lake," processor models in the series get numbered under Core Ultra 200 series.Intel will likely debut the lineup with overclocker-friendly K and KF SKUs. The lineup is led by the Core Ultra 9 285K (and possibly the 285KF), which comes with an 8P+16E core configuration, a processor base power value of 125 W, and a maximum P-core boost frequency of 5.50 GHz. This is followed by the Core Ultra 7 265K (and 265KF), with an 8P+12E core configuration; and the Core Ultra 5 245K, with a 6P+8E core-configuration.
There are also some 65 W non-K models in the middle, although these don't have similar processor model numbers to the K/KF parts. There's the Core Ultra 9 275 (8P+16E, 65 W); the Core Ultra 7 255 (8P+12E, 65 W); and the Core Ultra 5 240 (6P+4E, 65 W).
"Arrow Lake" is a chiplet-based processor, just like "Meteor Lake." Its compute tile, the piece of silicon with the CPU cores, packs up to 8 "Lion Cove" performance cores (P-cores), and up to 16 "Skymont" efficiency cores (E-cores). The processor is also expected to feature a 50 TOPS-class NPU for on-device AI acceleration, and a truncated version of the Xe-LPG iGPU the company is using with "Meteor Lake," which could be branded differently from the Arc Graphics branding Intel is using on the Core Ultra 100 series mobile chips. "Arrow Lake" is also expected to debut a new CPU socket on the desktop platform, the LGA1851, with more I/O capabilities than the LGA1700 and "Raptor Lake."
Sources:
BenchLife, VideoCardz
According to a report by Chinese tech publication Benchlife.info, the introduction of "Arrow Lake" would see Intel's desktop processor model numbering align with that of its mobile processor numbering, and incorporate the Core Ultra brand to denote the latest microarchitecture for a given processor generation. Since "Arrow Lake" is a generation ahead of "Meteor Lake," processor models in the series get numbered under Core Ultra 200 series.Intel will likely debut the lineup with overclocker-friendly K and KF SKUs. The lineup is led by the Core Ultra 9 285K (and possibly the 285KF), which comes with an 8P+16E core configuration, a processor base power value of 125 W, and a maximum P-core boost frequency of 5.50 GHz. This is followed by the Core Ultra 7 265K (and 265KF), with an 8P+12E core configuration; and the Core Ultra 5 245K, with a 6P+8E core-configuration.
There are also some 65 W non-K models in the middle, although these don't have similar processor model numbers to the K/KF parts. There's the Core Ultra 9 275 (8P+16E, 65 W); the Core Ultra 7 255 (8P+12E, 65 W); and the Core Ultra 5 240 (6P+4E, 65 W).
"Arrow Lake" is a chiplet-based processor, just like "Meteor Lake." Its compute tile, the piece of silicon with the CPU cores, packs up to 8 "Lion Cove" performance cores (P-cores), and up to 16 "Skymont" efficiency cores (E-cores). The processor is also expected to feature a 50 TOPS-class NPU for on-device AI acceleration, and a truncated version of the Xe-LPG iGPU the company is using with "Meteor Lake," which could be branded differently from the Arc Graphics branding Intel is using on the Core Ultra 100 series mobile chips. "Arrow Lake" is also expected to debut a new CPU socket on the desktop platform, the LGA1851, with more I/O capabilities than the LGA1700 and "Raptor Lake."
101 Comments on Core Configurations of Intel Core Ultra 200 "Arrow Lake-S" Desktop Processors Surface
Getting a 285K would be like adopting the i9-12900K. You get to experience the newest and the exciting, but you also deal with the whole truckload of bugs. I think if I'm purchasing CPUs out of necessity, i'm only going to be purchasing refined "tock" KS CPUs from here on out.
My brother's interested in upgrading as he's still rocking my old Zen 2 chip, it's a 3900XT but it's not really great anymore. Who knows, if the pricing on these Ultra chips is great and he wants my 13900KS, all he's gotta do is buy some DDR5 and it's his.
Let's see if they can release another Core 2.
Also wccftech say that "...the 40% rumor never talked about IPC and only talked about a specific SPEC result".
Being a TPU staff, I'd expect you to check your facts better before putting out blanket statements like this.
First of all, 'HT/SMT is not needed' is incorrect, regardless of core counts. It depends on the arch/workload.
Secondly, SMT will not automatically lower clocks/need higher voltages. Disabling SMT in a CPU that is designed with SMT in mind might allow higher clocks/lower voltages, but you lose performance and CPU utilization which in turn might allow those clocks. But if you design an arch without SMT, there are too many variables in play to determine whether clocks will actually increase or decrease. So no, not having SMT will not automatically increase clocks.
Security part is true, SMT does require added security measures. I guess given intel's track record it's probably a good thing they're not going to have HT.
Here's a link to one of his articles on SMT: www.anandtech.com/show/16261/investigating-performance-of-multithreading-on-zen-3-and-amd-ryzen-5000/5 I mean, the disadvantage of having cores with different ISA's are on an entirely different level compared to having two different CCD's with the same cores. Even having Zen4c's on a different CCD is better than intel's approach for pretty much any server workload and sometimes causes issues on the client side as well.
"all the same" isn't really the same.
I'd argue that the Ryzen 9 X3D's are the ones with an issue, considered the performance inconsistencies due to mismatched cache sizes across CCDs, cross-CCD latencies, eventual Infinity Fabric bottlenecks and of course, lacking the hardware thread scheduler entirely... and even that doesn't really matter to most workloads, these compromises are intentional from preventing the CPU from being a little too good on the AMD side.
Secondly, intel's hardware scheduler simply gives pointers to windows to schedule it correctly, but it doesn't work all the time as Darmok pointed out and there are other cases too. AMD doesn't face the same issue on workloads other than games. Ian did a deep dive into it but I think it was a podcast, I can't seem to find it in a pinch. AMD tried to go all software route for X3D, simply because the only thing they need to schedule strictly to the 8 cores are games, the rest of the workloads will perform similarly with the same scheduler used for the 7950x. So yeah, the game bar is finicky with older games and a solution similar to intel would work better for sure, but that's only for games. For the rest of workloads, they simply do not need a hardware scheduling pointer.
The intel 14th gen optimization tool was quite eye opening -- double % gains in some games with just software e-core optimizations; we are comparing early heterogeneous implementation to end stage HT/SMT...
All mobile devices, consumer devices... have been using heterogenous and AMD is moving there with Zen 6 too - because it actually works great. It's the only way intel was even able to stay competitive on an inferior node.
There's no competition
Regarding SMT, yeah for sure having a core that's better utilized without SMT will work better than one that 'needs' it to take advantage of the arch especially in the consumer space. Again, the server space is a different matter.
In the consumer space heterogenous architectures are pretty much the way forward, especially in laptops. I didn't state otherwise..