Tuesday, July 16th 2024
Intel Core Ultra 200 "Arrow Lake-S" Desktop Processor Core Configurations Surface
Intel is preparing a complete refresh of its desktop platform this year, with the introduction of the Core Ultra 200 series processors based on the "Arrow Lake" microarchitecture. The company skipped a desktop processor based on "Meteor Lake," probably because it didn't meet the desired multithreaded performance targets for Intel as it maxed out at 6P+8E+2LP, forcing Intel to come up with the 14th Gen Core "Raptor Lake Refresh" generation to see it through 2H-2023 and at least three quarters of 2024. The company, in all likelihood, will launch the new "Arrow Lake-S" Core Ultra 200 series toward late-Q3 or early-Q4 2024 (September-October). The first wave will include the overclocker-friendly K- and KF SKUs, alongside motherboards based on the top Intel Z890 chipset. 2025 will see the series ramp to more affordable processor models, and mainstream chipsets, such as the B860. These processors require a new motherboard, as Intel is introducing the new Socket LGA1851 with them.
Core configurations of the "Arrow Lake-S" chip surfaced on the web thanks to Jaykihn, a reliable source with Intel leaks. In its maximum configuration, the chip is confirmed to feature 8 P-cores, and 16 E-cores. There are no low-power island E-cores. Each of the 8 P-cores is a "Lion Cove" featuring 3 MB of dedicated L2 cache; while each the E-cores are "Skymont," arranged in 4-core modules that share 4 MB L2 caches among them. Intel claims that the "Lion Cove" P-core offers a 14% IPC increase over the "Redwood Cove" P-core powering "Meteor Lake," which in turn had either equal or a 1% IPC regression compared to "Raptor Cove." This would put "Lion Cove" at a 13-14% IPC advantage over the "Raptor Cove" cores. It's important to note here, that the "Lion Cove" P-cores lack HyperThreading, so Intel will be banking heavily on the "Skymont" E-cores to shore up generational multithreaded performance increase. "Skymont" was a show-stopper at Intel's Computex event, with a nearly 50% IPC gain over previous generations of Intel E-cores, which puts it at par with the "Raptor Cove" cores in single-thread performance.
On to the specific core-configurations, and it's no surprise that the Core Ultra 9 brand extension will max out the silicon, featuring an 8P+16E configuration. The Core Ultra 7 series will be 8P+12E.
The Core Ultra 5 series is subdivided into two—the K SKU will be based on the same B0 silicon as the Core Ultra 7 and Ultra 9 SKUs, and feature a 6P+8E configuration, whereas the other SKUs will be based on the C0 silicon. This is likely a physically smaller chip that only has a maximum of 6 P-cores and 8 E-cores, so Intel doesn't have to end up disabling two each of P-cores and E-core clusters to make them. Some of the non-K Core Ultra 5 SKUs will be 6P+8E, while the entry-level SKUs (such as the SKU that succeeds the current i5-14400) will be 6P+4E.
We have a theory that the C0 silicon not only has just 6 P-cores and 8 E-cores, but also smaller caches, such as 2.5 MB L2 cache per P-core, the way it is on "Lunar Lake."
The "Arrow Lake-S" desktop processor, for both the B0 and C0 dies, has an iGPU with just 4 Xe cores. The iGPU is based on the Xe2 "Battlemage" graphics architecture, but may lack the Arc Graphics branding, as these aren't quite meant for gaming. The 4 Xe cores would give the iGPU just 64 EU (execution units), or 512 unified shaders. This is still plenty of muscle for a non-gaming setup with two or more high-resolution (4K or 8K) monitors, which means the non-gaming desktop crowd is sufficiently covered with this iGPU.
The Core Ultra 9 series will likely lack a "KF" SKU, it will offer the iGPU with all 4 Xe cores (64 EU) enabled. The Core Ultra 7 series will have K and KF SKUs, the K SKUs will have the maxed out iGPU with 4 Xe cores, while the KF will have the iGPU disabled. The Core Ultra 5 K-series SKU will have the maxed out iGPU, the KF SKU will lack it; while things are s little different with the non-K/KF SKUs. The C0 silicon has the same iGPU as the B0, with 4 Xe cores available. Some of the upper Core Ultra 5 non-K SKUs will get 4 Xe Cores, the middle ones will get 3 Xe cores (48 EU), while the lower-end ones will get 2 Xe cores (32 EU).
Sources:
Jaykihn (Twitter), VideoCardz
Core configurations of the "Arrow Lake-S" chip surfaced on the web thanks to Jaykihn, a reliable source with Intel leaks. In its maximum configuration, the chip is confirmed to feature 8 P-cores, and 16 E-cores. There are no low-power island E-cores. Each of the 8 P-cores is a "Lion Cove" featuring 3 MB of dedicated L2 cache; while each the E-cores are "Skymont," arranged in 4-core modules that share 4 MB L2 caches among them. Intel claims that the "Lion Cove" P-core offers a 14% IPC increase over the "Redwood Cove" P-core powering "Meteor Lake," which in turn had either equal or a 1% IPC regression compared to "Raptor Cove." This would put "Lion Cove" at a 13-14% IPC advantage over the "Raptor Cove" cores. It's important to note here, that the "Lion Cove" P-cores lack HyperThreading, so Intel will be banking heavily on the "Skymont" E-cores to shore up generational multithreaded performance increase. "Skymont" was a show-stopper at Intel's Computex event, with a nearly 50% IPC gain over previous generations of Intel E-cores, which puts it at par with the "Raptor Cove" cores in single-thread performance.
The Core Ultra 5 series is subdivided into two—the K SKU will be based on the same B0 silicon as the Core Ultra 7 and Ultra 9 SKUs, and feature a 6P+8E configuration, whereas the other SKUs will be based on the C0 silicon. This is likely a physically smaller chip that only has a maximum of 6 P-cores and 8 E-cores, so Intel doesn't have to end up disabling two each of P-cores and E-core clusters to make them. Some of the non-K Core Ultra 5 SKUs will be 6P+8E, while the entry-level SKUs (such as the SKU that succeeds the current i5-14400) will be 6P+4E.
We have a theory that the C0 silicon not only has just 6 P-cores and 8 E-cores, but also smaller caches, such as 2.5 MB L2 cache per P-core, the way it is on "Lunar Lake."
The "Arrow Lake-S" desktop processor, for both the B0 and C0 dies, has an iGPU with just 4 Xe cores. The iGPU is based on the Xe2 "Battlemage" graphics architecture, but may lack the Arc Graphics branding, as these aren't quite meant for gaming. The 4 Xe cores would give the iGPU just 64 EU (execution units), or 512 unified shaders. This is still plenty of muscle for a non-gaming setup with two or more high-resolution (4K or 8K) monitors, which means the non-gaming desktop crowd is sufficiently covered with this iGPU.
The Core Ultra 9 series will likely lack a "KF" SKU, it will offer the iGPU with all 4 Xe cores (64 EU) enabled. The Core Ultra 7 series will have K and KF SKUs, the K SKUs will have the maxed out iGPU with 4 Xe cores, while the KF will have the iGPU disabled. The Core Ultra 5 K-series SKU will have the maxed out iGPU, the KF SKU will lack it; while things are s little different with the non-K/KF SKUs. The C0 silicon has the same iGPU as the B0, with 4 Xe cores available. Some of the upper Core Ultra 5 non-K SKUs will get 4 Xe Cores, the middle ones will get 3 Xe cores (48 EU), while the lower-end ones will get 2 Xe cores (32 EU).
55 Comments on Intel Core Ultra 200 "Arrow Lake-S" Desktop Processor Core Configurations Surface
Never understand why they change the socket type very often.
C0 stepping is really interesting, perhaps 20A. and B0 is N3. It means all K-models are N3.
What we don't know is how exactly HT is implemented on Intel side. In the recent interview with AMD's Mike Clark on Chips and Cheese Zen's SMT implementation was described and it turns out that a single thread can utilize almost everything in the core for itself because there's barely any static partitioning. Removing SMT from Zen wouldn't shrink the core.
Maybe Intel's implementation is so much different that removing HT actually shrinks the core or provides a tangible gain in efficiency? Or Intel isn't too thrilled to have complex scheduling requirements for the OS, having to deal with P-cores, HT on P-cores, E-cores with their clusters and LPE-cores like on Meteor Lake?
+ 8 of these:If all pans out I'll get an Ultra 9 for my next build!
Sure, e-cores are useless, just disable them..... :laugh:
videocardz.com/newz/intel-core-ultra-9-285k-rumored-to-boost-up-to-5-7-ghz
So single thread improvement is in the 5-10% range.
However, is it certain by now that Intel is getting rid of HT in desktop CPUs, or did averybody just infer that from the fact that Lunar Lake lacks it?
I think HT and SMT will be fading away has the manufactoring nodes improves... even games prefer "cores" instead of "HT/SMT threads"...
A key reason for bringing Hyper-Threading to an end could be related, explicitly, to the rise in core counts on modern CPUs.
In short, having a greater raw number of cores minimizes the advantages of Hyper-Threading.
The problem with HT has been the ongoing serious security issues that reduce performance once corrected.
No need to cheerlead or excuse a company’s clock speed decisions.
The SMT will always be an important feature.
We will see how the top Ultra 9 28-thread will compete with the 32-thread Ryzen 9.