AMD "Zen 3" microarchitecture could be designed for the enhanced 7 nm+ EUV (extreme ultraviolet) silicon fabrication node at TSMC, which promises a significant 20 percent increase in transistor densities compared to the 7 nm DUV (deep ultraviolet) node on which its "Zen 2" processors are being built. In addition, the node will also reduce power consumption by up to 10 percent at the same operational load. In a late-2018 interview, CTO Mark Papermaster stated AMD's design goal with "Zen 3" would be to prioritize energy-efficiency, and that it would present "modest" performance improvements (read: IPC improvements) over "Zen 2." AMD made it clear that it won't drag 7 nm DUV over more than one microarchitecture (Zen 2), and that "Zen 3" will debut in 2020 on 7 nm+ EUV.

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today announced that its 5-nanometer (nm) FinFET process technology is complete in its development and is now ready for customers' samples. By adding another cutting-edge node to its extreme ultraviolet (EUV)-based process offerings, Samsung is proving once again its leadership in the advanced foundry market.

Compared to 7 nm, Samsung's 5 nm FinFET process technology provides up to a 25 percent increase in logic area efficiency with 20 percent lower power consumption or 10 percent higher performance as a result of process improvement to enable us to have more innovative standard cell architecture. In addition to power performance area (PPA) improvements from 7 nm to 5 nm, customers can fully leverage Samsung's highly sophisticated EUV technology. Like its predecessor, 5 nm uses EUV lithography in metal layer patterning and reduces mask layers while providing better fidelity.

TSMC announced they've completed the infrastructure design for the 5 nm process, which is the next step in silicon evolution when it comes to density and performance. TSMC's 5 nm process will leverage the company's second implementation of EUV (Extreme Ultra Violet) technology (after it's integrated in their 7 nm process first), allowing for improved yields and performance benefits.

According to TSMC, the 5 nm process will enable up to 1.8x the logic density of their 7 nm process, a 15% clock speed gain due to process improvements alone on an example Arm Cortex-A72 core, as well as SRAM and analog circuit area reduction, which means higher number of chips per wafer. The process is being geared for mobile, internet, and high performance computing applications. TSMC also provides online tools for silicon design flow scenarios that are optimized for their 5 nm process. Risk production is already ongoing.

TAITRA, the governing body behind the annual Computex trade-show held in Taipei each June, announced that AMD CEO Dr. Lisa Su will host a keynote address which promises to be as exciting as her CES keynote. It is revealed that Dr. Su will simultaneously launch or unveil at least four product lines. High up the agenda is AMD's highly anticipated 3rd generation Ryzen desktop processors in the socket AM4 package, based on "Zen 2" microarchitecture, and a multi-chip module (MCM) codenamed "Matisse." This launch could be followed up by a major announcement related to the company's 2nd generation EPYC enterprise processors based on the "Rome" MCM.

PC enthusiasts are in for a second major announcement, this time from RTG, with a technical reveal or unveiling of Radeon "Navi," the company's first GPU designed from the ground up for the 7 nm silicon fabrication process. It remains to be seen which market-segment AMD targets with the first "Navi" products, and the question on everyone's minds, whether AMD added DXR acceleration, could be answered. Lastly, the company could announce more variants of its Radeon Instinct DNN accelerators.

Taiwan External Trade Development Council (TAITRA) announced today that the 2019 COMPUTEX International Press Conference will be held with a Keynote by AMD President and CEO Dr. Lisa Su. The 2019 COMPUTEX International Press Conference & CEO Keynote is scheduled for Monday, May 27 at 10:00 AM in Room 201 of the Taipei International Convention Center (TICC) in Taipei, Taiwan with the keynote topic "The Next Generation of High-Performance Computing".

"COMPUTEX, as one of the global leading technology tradeshows, has continued to advance with the times for more than 30 years. This year, for the first time, a keynote speech will be held at the pre-show international press conference," said Mr. Walter Yeh, President & CEO, TAITRA, "Dr. Lisa Su received a special invitation to share insights about the next generation of high-performance computing. We look forward to her participation attracting more companies to participate in COMPUTEX, bringing the latest industry insights, and jointly sharing the infinite possibilities of the technology ecosystem on this global stage."

AMD will launch its 3rd generation Ryzen 3000 Socket AM4 desktop processors in 2019, with a product unveiling expected mid-year, likely on the sidelines of Computex 2019. AMD is keeping its promise of making these chips backwards compatible with existing Socket AM4 motherboards. To that effect, motherboard vendors such as ASUS and MSI began rolling out BIOS updates with AGESA-Combo 0.0.7.x microcode, which adds initial support for the platform to run and validate engineering samples of the upcoming "Zen 2" chips.

At CES 2019, AMD unveiled more technical details and a prototype of a 3rd generation Ryzen socket AM4 processor. The company confirmed that it will implement a multi-chip module (MCM) design even for their mainstream-desktop processor, in which it will use one or two 7 nm "Zen 2" CPU core chiplets, which talk to a 14 nm I/O controller die over Infinity Fabric. The two biggest components of the IO die are the PCI-Express root complex, and the all-important dual-channel DDR4 memory controller. We bring you never before reported details of this memory controller.

NVIDIA will kick off the 2019 GPU Technology Conference later today, at 2 PM Pacific time. The company is expected to either tease or unveil a new graphics architecture succeeding "Volta" and "Turing." Not much is known about this architecture, but it's highly likely to be NVIDIA's first to be designed for the 7 nm silicon fabrication process. This unveiling could be the earliest stage of the architecture's launch cycle, would could see market availability only by late-2019 or mid-2020, if not later, given that the company's RTX 20-series and GTX 16-series have only been unveiled recently. NVIDIA could leverage 7 nm to increase transistor densities, and bring its RTX technology to even more affordable price-points.

GlobalFoundries is looking to be sold lock-stock-and-barrel by its investors, after heavily downsizing and parting with some of its Singapore-based assets recently. Once promising to lead the market with 7 nm and 5 nm advancements, the company crashed out of the sub-10 nm race, making AMD, its biggest customer, look for 7 nm supplies from TSMC. GlobalFoundries is the world's third largest semiconductor foundry service provider, with an 8.4 percent market share, behind TSMC and Samsung. Intel doesn't offer manufacturing services, as its fabs are fully dedicated to manufacturing its own products.

GlobalFoundries's main investor is Abu Dhabi-based Mubadala Technology, which holds a 90 percent stake in the company. Korean semiconductor companies Samsung and SK Hynix are reportedly in the foray to buy out GlobalFoundries, as it would give them a turnkey presence in the US, with its Upstate New York facilities. The company is unlikely to entertain bids from Chinese companies, as CFIUS would likely block the sale. "Global Foundries is unlikely to be bought by a Chinese company such as SMIC in that the U.S. government is keeping China in check in various industries," said an industry insider, adding, "The most potential candidates include South Korean companies such as Samsung Electronics and SK Hynix, and Samsung Electronics can increase its share in the market to 23 percent at once if it takes over Global Foundries."

TSMC is giving final touches to set its flagship 7 nanometer EUV (extreme ultraviolet lithography) silicon fabrication node at its highest state of readiness for business, called mass-production. At this state, the node can mass-produce products for TSMC's customers. TSMC had taped out its first 7 nm EUV chips in October 2018. The company will also begin risk-production of the more advanced 5 nm node in April, staying on schedule. Mass production of 5 nm chips could commence in the first half of 2020.

The 7 nm EUV node augments TSMC's 7 nm DUV (deep ultraviolet lithography) node that's been already active since April 2018, and producing chips for AMD, Apple, HiSilicon, and Xilinx. At the turn of the year, 7 nm DUV made up 9 percent of TSMC's shipments. With the new node going online, 7 nm (DUV + EUV) could make up 25 percent of TSMC's output by the end of 2019.

AMD "Navi" is the company's next-generation graphics architecture succeeding "Vega" and will leverage the 7 nm silicon fabrication process. It was originally slated to launch mid-2019, with probable unveiling on the sidelines of Computex (early-June). Cowcotland reports that AMD has delayed its plans to launch "Navi" all the way to October (Q4-2019). The delay probably has something to do with AMD's 7 nm foundry allocation for the year.

AMD is now fully reliant on TSMC to execute its 7 nm product roadmap, which includes its entire 2nd generation EPYC and 3rd generation Ryzen processors based on the "Zen 2" architecture, and to a smaller extent, GPUs based on its 2nd generation "Vega" architecture, such as the recently launched Radeon VII. We expect the first "Navi" discrete GPU to be a lean, fast-moving product that succeeds "Polaris 30." In addition to 7 nm, it could incorporate faster SIMD units, higher clock-speeds, and a relatively cost-effective memory solution, such as GDDR6.

GIGABYTE, the world's leading premium gaming hardware manufacturer, today announced the launch of Radeon VII HBM2 16G, the latest Radeon VII graphics cards built upon the world's first 7nm gaming GPU. Based on the enhanced second-generation AMD 'Vega' architecture, Radeon VII is equipped with 3840 stream processors and 16GB of ultra-fast HBM2 memory (second-generation High-Bandwidth Memory). It is designed to deliver exceptional performance and amazing experiences for the latest AAA, e-sports and Virtual Reality (VR) titles, demanding 3D rendering and video editing applications, and next-generation compute workloads.

According to the AMD official website, the Radeon VII graphics card enables high-performance gaming and ultra-high quality visuals. Ground-breaking 1 TB/s memory bandwidth and a 4,096-bit memory interface paves the way for ultra-high resolution textures, hyper-realistic settings and life-like characters. With the high speeds of today's graphics cards, framerates often exceed the monitor refresh rate, causing stuttering and tearing.

AMD in its Q4-2018 Earnings Report disclosed that it has amended its Wafer Supply Agreement (WSA) with GlobalFoundries that frees it from paying a "7 nanometer tax." Under the older version of WSA, AMD would have had to pay a penalty to GlobalFoundries if it sourced processors from any other semiconductor foundry. The company got preferential pricing in return for the exclusivity. With GlobalFoundries discontinuing development of cutting-edge processes such as 7 nm and 5 nm, it makes sense for AMD to seek out other foundry partners, such as TSMC, and an amendment to the WSA was needed. With this amendment in place, AMD can go ahead and source 7 nm dies from TSMC without paying penalties to GlobalFoundries (GloFo).

With its "Zen 2" microarchitecture, AMD is going big on multi-chip modules, in which only those components that can tangibly benefit from the switch to the 7 nm node, namely the CPU cores, would be built on 7 nm dies, called "CPU chiplets," while components that don't need the miniaturization just yet, such as the processor's memory controller, PCIe root-complex, etc., will be built on separate dies called "I/O controllers." These dies will continue to be 14 nm, and likely supplied by GloFo. Final packaging of 7 nm CPU chiplets from TSMC, and 14 nm I/O controllers from GloFo, will happen at GloFo's facilities in China or Malaysia. AMD in its amendment committed to purchasing 14 nm and 12 nm chips from GloFo between 2019 and 2021, which means the MCM approach to processors is here to stay.

TSMC's introduction of its 7 nm fabrication technology has essentially propelled the company to silicon manufacturing heights. Every company - particularly in the mobile space - is after the most minute increase in transistor density and power consumption improvements the latest and greatest can bring. AMD themselves have become a major TSMC partner in pursuit of its newfound competitiveness against Intel, and has apparently leveraged the 7 nm process as a way to keep its high-performance GPU offering minimally competitive with NVIDIA's solution - at a much lesser die area requirement, if the Radeon VII vs RTX 2080 estimates are something to go by.

As a consequence of the market interest for the 7 nm process, it has rapidly become TSMC's biggest revenue generator as soon as 4Q18. The company said that 7 nm already generated 10% of the company's entire 2018 revenue, despite the process only having been ramped up in June of the same year. Other less dense technologies still generate a lot of revenue for the company, and are likely much higher volume. However, TSMC is most likely riding on much increased ASP for 7 nm wafers than for other technologies.

A report via Tom's Hardware.de says that AMD's plans for the upcoming Radeon VII are somewhat one-dimensional, in that only reference designs will be available for this particular rendition of the Vega architecture. And this doesn't mean"initial availability" only on reference cards, like NVIDIA has been doing with their Founder's editions; the report claims that at no point in time will there actually be a custom-designed Radeon VII. The quantity of Radeon VII GPUs will apparently be "strictly limited" come launch - a likely result of the decision to make use of TSMC's 7 nm process, which will have to serve not only AMD's Ryzen 3000 and Epyc CPUs when those are actually launched, but all of TSMC's other clients.

This is in contrast with AMD CEO Lisa Su's words during her CES keynote, who said that Radeon VII would be available from "several leading add-in board partners plan to offer the cards". According to a Tom's Hardware.de Taiwanese source, "You cannot leak anything that does not exist" in regards to third-party designs. And another Chinese source said "the quantity of Radeon VII is strictly limited… not sure if AMD wants to open AIB to have an own design later".

AMD's CTO Mark Papermaster, in an interview with TheStreet, confirmed AMD's plans with 7 nm for their graphics offerings are just beginning with Radeon VII. When inquired on AMD's plans for their graphics division, Papermaster said that "What we do over the course of the year is what we do every year. We'll round out the whole roadmap." he then added that "We're really excited to start on the high-end... you'll see the announcements over the course of the year as we round out our Radeon roadmap."

So these comments form papermaster seemingly confirm two things: first, that AMD plans to "round out" its lineup using the 7 nm process technology, which means increasing offerings at different price points. The use of the word "refresh" almost takes the breath away, since refreshes are usually based on the same previous architectures. However, AMD does have plans for a new mid-range chip to finally succeed Polaris in Navi, which should become the next AMD launch in the 7 nm process for graphics technologies.

AMD pulled off a surprise at its CES 2019 keynote address, with the announcement of the Radeon VII client-segment graphics card targeted at gamers. We went hands-on with the card earlier this week. The company revealed a few more technical details of the card in its press-deck for the card. To begin with, the company talks about the immediate dividends of switching from 14 nm to 7 nm, with a reduction in die-size from 495 mm² on the "Vega 10" silicon to 331 mm² on the new "Vega 20" silicon. The company has reworked the die to feature a 4096-bit wide HBM2 memory interface, the "Vega 20" MCM now features four 32 Gbit HBM2 memory stacks, which make up the card's 16 GB of memory. The memory clock has been dialed up to 1000 MHz from 945 MHz on the RX Vega 64, which when coupled with the doubled bus-width, works out to a phenomenal 1 TB/s memory bandwidth.

We know from AMD's late-2018 announcement of the Radeon Instinct MI60 machine-learning accelerator based on the same silicon that "Vega 20" features a total of 64 NGCUs (next-generation compute units). To carve out the Radeon VII, AMD disabled 4 of these, resulting in an NGCU count of 60, which is halfway between the RX Vega 56 and RX Vega 64, resulting in a stream-processor count of 3,840. The reduced NGCU count could help AMD harvest the TSMC-built 7 nm GPU die better. AMD is attempting to make up the vast 44 percent performance gap between the RX Vega 64 and the GeForce RTX 2080 with a combination of factors.

NVIDIA will implement the 7 nanometer EUV (extreme ultraviolet) lithography to build its future generation of GPUs slated for 2020, according to Japanese publication MyNavi.jp. The GPU giant could be among the first customers besides IBM, to contract Samsung for 7 nm EUV mass-production of GPUs. IBM will use the Korean semiconductor giant for manufacturing Z-series processors and FPGAs. Samsung announced in October 2018 that it will begin risk-production on its 7 nm EUV node in early-2019.

An earlier report from 2018 also forecast NVIDIA implementing 7 nm DUV (deep ultraviolet) node of TSMC for its 2019 GPU lineup. With news of the company now working with Samsung on 7 nm EUV for 2020, this seems less likely. It's possible that NVIDIA could somehow split its next generation GPU lineup between TSMC 7 nm DUV and Samsung 7 nm EUV, with the latter being used for chips with higher transistor-counts, taking advantage of the node's higher deliverable transistor densities.

IBM today announced an agreement with Samsung to manufacture 7-nanometer (nm) microprocessors for IBM Power Systems , IBM Z and LinuxONE , high-performance computing (HPC) systems, and cloud offerings. The agreement combines Samsung's industry-leading semiconductor manufacturing with IBM's high-performance CPU designs. This combination is being designed to drive unmatched systems performance, including acceleration, memory and I/O bandwidth, encryption and compression speed, as well as system scaling. It positions IBM and Samsung as strategic partners leading the new era of high-performance computing specifically designed for AI.

"At IBM, our first priority is our clients," said John Acocella, Vice President of Enterprise Systems and Technology Development for IBM Systems. "IBM selected Samsung to build our next generation of microprocessors because they share our level of commitment to the performance, reliability, security, and innovation that will position our clients for continued success on the next generation of IBM hardware."

AMD late November filed a trademark application with the USPTO for a new logo, for its second generation "Vega" graphics architecture, built around the 7 nm silicon fabrication process. The logo looks similar to the original Vega "V," with two bands marking out the Roman numeral II (2). This logo could appear on the product and marketing on a series of new Radeon Pro and Radeon Instinct (and possibly even gaming-grade Radeon RX?) graphics cards based on AMD's new "Vega 20" multi-chip module. This chip features a doubling in memory bandwidth thanks to its 4096-bit wide HBM2 interface, and the optical shrink of the GPU die to the 7 nm node could enable AMD to dial up engine clocks significantly.

There could be light at the end of the tunnel for Intel's silicon fabrication business after all, as the company reported that its 7 nanometer silicon fabrication node, which incorporates EUV (extreme ultraviolet) lithography, is on track. The company stressed in its Nasdaq Investors' Conference presentation that its 7 nm EUV process is de-linked from its 10 nm DUV (deep ultraviolet) node, and that there are separate teams working on their development. The 10 nm DUV node is qualitatively online, and is manufacturing small batches of low-power mobile "Cannon Lake" Core processors.

Cannon Lake is an optical shrink of the "Skylake" architecture to the 10 nm node. Currently there's only one SKU based on it, the Core i3-8121U. Intel utilized the electrical gains from the optical shrink to redesign the client-segment architecture's FPU to support the AVX-512 instruction-set (although not as feature-rich as the company's enterprise-segment "Skylake" derivatives). The jump from 10 nm DUV to 7 nm EUV will present a leap in transistor densities, with Intel expecting nothing short of a doubling. 10 nm DUV uses a combination of 193 nm wavelength ultraviolet lasers and multi-patterning to achieve its transistor density gains over 14 nm++. The 7 nm EUV node uses an extremely advanced 135 nm indirect laser, reducing the need for multi-patterning. The same laser coupled with multi-patterning could be Intel's ticket to 5 nm.

DigiTimes, citing a Chinese-language Commercial Times report, cites TSMC's 7 nm foundry capacity as likely being underutilized in 2019. After TSMC announced it expected cutting-edge 7 nm designs to correspond to around 20% of the company's revenues in 2019, the company will likely have to review those projections, as lower demand from smartphone chip manufacturers will likely leave TSMC with less actual output than that which it can churn out.

Due to a cutback in orders placed by Apple, HiSilicon and Qualcomm, concerns regarding TSMC's ability to be the sole 7 nm chip fabrication tech for the industry can likely be laid to rest. That the smartphone market is reaching saturation is a well-known quantity - it's becoming harder and harder to cram new technologies that justify the yearly smartphone upgrade that most companies vie for - and one of the reasons for the launch of various brand-specific smartphone subscription services. The difference isn't scandalous - TSMC will still be making use of 80-90% of its total 7nm process capacity during the first half of 2019, the report quoted industry sources as saying.

A SiSoft SANDRA results database entry for a 2P AMD "Rome" EPYC machine sheds light on the lower cache hierarchy. Each 64-core EPYC "Rome" processor is made up of eight 7 nm 8-core "Zen 2" CPU chiplets, which converge at a 14 nm I/O controller die, which handles memory and PCIe connectivity of the processor. The result mentions cache hierarchy, with 512 KB dedicated L2 cache per core, and "16 x 16 MB L3." Like CPU-Z, SANDRA has the ability to see L3 cache by arrangement. For the Ryzen 7 2700X, it reads the L3 cache as "2 x 8 MB L3," corresponding to the per-CCX L3 cache amount of 8 MB.

For each 64-core "Rome" processor, there are a total of 8 chiplets. With SANDRA detecting "16 x 16 MB L3" for 64-core "Rome," it becomes highly likely that each of the 8-core chiplets features two 16 MB L3 cache slices, and that its 8 cores are split into two quad-core CCX units with 16 MB L3 cache, each. This doubling in L3 cache per CCX could help the processors cushion data transfers between the chiplet and the I/O die better. This becomes particularly important since the I/O die controls memory with its monolithic 8-channel DDR4 memory controller.

Intel is reportedly working tirelessly to launch its "Cascade Lake" Xeon Scalable 48-core enterprise processor before year-end, according to a launch window timeline slide leaked by datacenter hardware provider QCT. The slide suggests a late-Q4 thru Q1-2019 launch timeline for the XCC (extreme core count) version of "Cascade Lake," which packs 48 CPU cores across two dies on an MCM. This launch is part of QCT's "early shipment program," which means select enterprise customers can obtain the hardware in pre-approved quantities. In other words, this is a limited launch, but one that's probably enough to upstage AMD's 7 nm EPYC "Rome" 64-core processor launch.

It's only by late-Q1 thru Q2-2019 that the Xeon "Cascade Lake" family would be substantially launched, including lower core-count variants that are still 2-die MCMs. This aligns to preempt or match AMD's 7 nm EPYC family rollout through 2019. "Cascade Lake" is probably Intel's final enterprise microarchitecture to be built on the 14 nm++ node, and consists of 2-die multi-chip modules that feature 48 cores, and a 12-channel memory interface (6-channel per die); with 88-lane PCIe from the CPU socket. The processor is capable of multi-socket configurations. It will also be Intel's launch platform for substantially launching its Optane Persistent Memory product series.

AMD recently announced the Radeon Instinct MI60, a GPU-based data-center compute processor with hardware virtualization features. It takes the crown for "the world's first 7 nm GPU." The company also put out specifications of the "Vega 20" GPU it's based on: 4,096 stream processors, 4096-bit HBM2 memory interface, 1800 MHz engine clock-speed, 1 TB/s memory bandwidth, 7.4 TFLOP/s peak double-precision (FP64) performance, and the works. Here's the kicker: the company isn't launching this accelerator with Windows support. At launch, AMD is only releasing x86-64 Linux drivers, with API support for OpenGL 4.6, Vulkan 1.0, and OpenCL 2.0, along with AMD's ROCm open ecosystem. The lack of display connector already disqualifies this card for most workstation applications, but with the lack of Windows support, it is also the most expensive graphics card that "can't run Crysis." AMD could release Radeon Pro branded graphics cards based on "Vega 20," which will ship with Windows and MacOS drivers.

Here is the clearest picture of AMD "Rome," codename for the company's next-generation EPYC socket SP3r2 processor, which is a multi-chip module of 9 chiplets (up from four). While first-generation EPYC MCMs (and Ryzen Threadripper) were essentially "4P-on-a-stick," the new "Rome" MCM takes the concept further, by introducing a new centralized uncore component called the I/O die. Up to eight 7 nm "Zen 2" CPU dies surround this large 14 nm die, and connect to it via substrate, using InfinityFabric, without needing a silicon interposer. Each CPU chiplet features 8 cores, and hence we have 64 cores in total.

The CPU dies themselves are significantly smaller than current-generation "Zeppelin" dies, although looking at their size, we're not sure if they're packing disabled integrated memory controllers or PCIe roots anymore. While the transition to 7 nm can be expected to significantly reduce die size, groups of two dies appear to be making up the die-area of a single "Zeppelin." It's possible that the CPU chiplets in "Rome" physically lack an integrated northbridge and southbridge, and only feature a broad InfinityFabric interface. The I/O die handles memory, PCIe, and southbridge functions, featuring an 8-channel DDR4 memory interface that's as monolithic as Intel's implementations, a PCI-Express gen 4.0 root-complex, and other I/O.