Fujitsu has today officially completed the delivery of the Fugaku supercomputer to the Riken scientific research institute of Japan. This is a big accomplishment as the current COVID-19 pandemic has delayed many happenings in the industry. However, Fujitsu managed to play around that and deliver the supercomputer on time. The last of 400 racks needed for the Fugaku supercomputer was delivered today, on May 13th, as it was originally planned. The supercomputer is supposed to be fully operational starting on the physical year of 2021, where the installation and setup will be done before.

As a reminder, the Fugaku is an Arm-based supercomputer consisting out of 150 thousand A64FX CPUs. These CPUs are custom made processors by Fujitsu based on Arm v8.2 ISA, and they feature 48 cores built on TSMC 7 nm node and running above 2 GHz. Packing 8.786 billion transistors, this monster chips use HBM2 memory instead of a regular DDR memory interface. Recently, a prototype of the Fugaku supercomputer was submitted to the Top500 supercomputer list and it came on top for being the most energy-efficient of all, meaning that it will be as energy efficient as it will be fast. Speculations are that it will have around 400 PetaFlops of general compute power for Dual-Precision workloads, however, for the specific artificial intelligence applications, it should achieve ExaFLOP performance target.

It was only a matter of time before AMD brought its 7 nm "Renoir" APU silicon onto the desktop platform. The first such chip just hit the radar as the Ryzen 7 4700G. This would be the first desktop Ryzen APU graded as Ryzen 7, thanks to its CPU core count. The 4700G features an 8-core/16-thread CPU based on the "Zen 2" microarchitecture. The iGPU is a hybrid between "Vega" and "Navi."

The "Renoir" iGPU features the SIMD components of "Vega," but with the display- and multimedia-engines of "Navi." The iGPU apparently maxes out on 8 NGCUs on "Renoir," amounting to 512 stream processors. Increased iGPU engine clocks attempt to make up the CU deficit compared to the previous-generation "Picasso" (8 vs. 11). The CPU features 512 KB of L2 cache per core, and 8 MB of shared L3 cache (4 MB per CCX). An AoTS run in which the processor is paired with a Radeon RX 5700 XT graphics card surfaced on social media. Bringing "Renoir" to the desktop platform at prices competitive with Intel's 10th generation Core i3 thru Core i7 will be critical for AMD, as it nullifies a key advantage Intel has - integrated graphics, so the processors could make it to the vast majority of non-gaming builds with high CPU performance demand.Update May 10th: A possible UserBenchmark submission of this processor, where it carries the engineering sample number "100-000000149-40_40/30_Y" surfaced. It's shown having clock speeds of 3.00 GHz base and 4.00 GHz boost. We know this is a desktop platform looking at its ASRock B550 Taichi motherboard and Micron-supplied standard DIMM.

Today, AMD announced global availability of the world's first x86 7 nm commercial notebook processors, the AMD Ryzen PRO 4000 Series Mobile family, delivering the most cores and threads in an ultrathin business notebook. These new processors are fully optimized for remote work capabilities and designed to take business computing to the next level with multi-threading performance for modern productivity. Robust enterprise designs from HP and Lenovo powered by AMD Ryzen PRO 4000 Series Mobile Processors are expected to be available worldwide starting in the first half of 2020, with anywhere-anytime productivity, multiple layers of security features, seamless manageability and reliable longevity.

"With the launch of AMD Ryzen PRO 4000 Series Mobile Processors, AMD once again defines the new standard for PC experiences - from high-end desktop computing to ultrathin and gaming notebooks, and now the modern business notebook," said Saeid Moshkelani, senior vice president and general manager, client business unit, AMD. "Built on the ground-breaking "Zen 2" architecture and 7 nm process technology, the AMD Ryzen for Business portfolio delivers advanced performance, reliable security features, impressive battery life and advanced manageability to significantly elevate the capabilities of the ultrathin notebook in any work environment."

A DigiTimes premium report, interpreted by Chiakokhua, aka Retired Engineer, chronicling NVIDIA's move to contract TSMC for 7 nm and 5 nm EUV nodes for GPU manufacturing, made a startling revelation about NVIDIA's recent foundry diversification moves. Back in July 2019, a leading Korean publication confirmed NVIDIA's decision to contract Samsung for its next-generation GPU manufacturing. This was a week before AMD announced its first new-generation 7 nm products built for the TSMC N7 node, "Navi" and "Zen 2." The DigiTimes report reveals that NVIDIA underestimated the efficiency gains AMD would yield from TSMC N7.

With NVIDIA's bonhomie with Samsung underway, and Apple transitioning to TSMC N5, AMD moved in to quickly grab 7 nm-class foundry allocation and gained prominence with the Taiwanese foundry. The report also calls out a possible strategic error on NVIDIA's part. Upon realizing the efficiency gains AMD managed, NVIDIA decided to bet on TSMC again (apparently without withdrawing from its partnership with Samsung), only to find that AMD had secured a big chunk of its nodal allocation needed to support its growth in the x86 processor and discrete GPU markets. NVIDIA has hence decided to leapfrog AMD by adapting its next-generation graphics architectures to TSMC's EUV nodes, namely the N7+ and N5. The report also speaks of NVIDIA using its Samsung foundry allocation as a bargaining chip in price negotiations with TSMC, but with limited success as TSMC established its 7 nm-class industry leadership. As it stands now, NVIDIA may manufacture its 7 nm-class and 5 nm-class GPUs on both TSMC and Samsung.

TSMC has reportedly secured orders from NVIDIA for chips based on its 7 nm and 5 nm silicon fabrication nodes, sources tell DigiTimes. If true, it could confirm rumors of NVIDIA splitting its next-generation GPU manufacturing between TSMC and Samsung. The Korean semiconductor giant is commencing 5 nm EUV mass production within Q2-2020, and NVIDIA is expected to be one of its customers. NVIDIA is expected to shed light on its next-gen graphics architecture at the GTC 2020 online event held later this month. With its "Turing" architecture approaching six quarters of market presence, it's likely that the decks are being cleared for a new architecture not just in HPC/AI compute product segment, but also GeForce and Quadro consumer graphics cards. Splitting manufacturing between TSMC and Samsung would help NVIDIA disperse any yield issue arriving from either foundry's EUV node, and give it greater bargaining power with both.

Silicon Valley startup Tachyum, founded in 2016, is ready with its crowning product, the Tachyum Prodigy. The startup recently received an investment from the Slovak government in hopes of job-creation in the country. The Prodigy is what its makers call "a universal processor," which "outperforms the fastest Xeon at 10X lower power." The company won't mention what machine architecture it uses (whether it's Arm or MIPS, or its own architecture). Its data-sheet is otherwise full of specs that scream at you.

To begin with, its top trim, the Prodigy T16128, packs 128 cores on a single package, complete with 64-bit address space, 512-bit vector extensions, matrix multiplication fixed-function hardware that accelerate AI/ML, and 4 IPC at up to 4.00 GHz core clock. Tachyum began the processor's software-side support, with an FPGA emulator in December 2019 (so you can emulate the processor on an FPGA and begin developing for it), C/C++ and Fortran compilers; debuggers and profilers, tensorflow compilers, and a Linux distribution that's optimized it. The I/O capabilities of this chip are something else.

AMD in its post Q1-2020 earnings release disclosures stated that the company is "on track" to launching its next-generation "Zen 3" CPU microarchitecture and RDNA2 graphics architecture in late-2020. The company did not reveal in what shape or form the two will debut. AMD is readying "Zen 3" based EPYC "Milan" enterprise processors, "Vermeer" Ryzen desktop processors, and "Cezanne" Ryzen mobile APUs based on "Zen 3," although there's no word on which product line the microarchitecture will debut with. "Zen 3" compute dies (CCDs) are expected to do away with the quad-core compute complex (CCX) arrangement of cores, and are expected to be built on a refined 7 nm-class silicon fabrication process, either TSMC N7P or N7+.

The only confirmed RDNA2 based products we have as of now are the semi-custom SoCs that drive the Sony PlayStation 5 and Microsoft Xbox Series X next-generation consoles, which are expected to debut by late-2020. The AMD tweet, however, specifies "GPUs" (possibly referring to discrete GPUs). Also, with AMD forking its graphics IP to RDNA (for graphics processors) and CDNA (for headless compute accelerators), we're fairly sure AMD is referring to a Radeon RX or Radeon Pro launch in the tweet. Microsoft's announcement of the DirectX 12 Ultimate logo is expected to expedite launch of Radeon RX discrete GPUs based on RDNA2, as the current RDNA architecture doesn't meet the logo requirements.

Intel's first client-segment processor microarchitecture built on its own 7 nm silicon fabrication process will be codenamed "Meteor Lake." The codename began surfacing in driver files and technical documents, one of which was screengrabbed and leaked to the web by Komachi Ensaka. Not much else is known about it, except that it succeeds the 10 nm++ "Alder Lake," an ambitious attempt by Intel to replicate Arm big.LITTLE heterogenous core technology on the x86 architecture, by combining a number of high-power cores with high-efficiency cores on a single piece of silicon. Intel "Lakefield," headed toward mass-production within this year, is the first such heterogenous core.

Older reports throughout 2019-20 speculate "Meteor Lake" (known at the time only by its name), could come out at a time when Intel monetizes its "Golden Cove" high-performance CPU core. It's quite likely that like "Alder Lake," it could be a heterogenous chip targeting several client form-factors, mobile and desktop. The company could leverage its 7 nm process - claimed to rival TSMC 5 nm-class in transistor density - in turning up core-counts over "Alder Lake." We'll learn more about "Meteor Lake" as we crawl toward its 2022 launch window, if it still holds up.

A report via DigiTimes places TSMC as having announced to its investors that exploratory studies and R&D for the development of the 2 nm process node have commenced. As today's leading semiconductor fabrication company, TSMC doesn't seem to be one resting on its laurels. Their 7 nm process and derivatives have already achieved a 30% weight on the company's semiconductor orders, and their 5 nm node (which will include EUV litography) is set to hit HVM (High Volume Manufacturing) in Q2 of this year. Apart from that, not much more is known on 2 nm.

After 5 nm, which is expected to boats of an 84-87% transistor density gain over the current 7nm node, the plans are to go 3nm, with TSMC expecting that node to hit mass production come 2022. Interestingly, TSMC is planning to still use FinFET technology for its 3 nm manufacturing node, though in a new GAAFET (gate-all-around field-effect transistor) technology. TSMC's plans to deploy FinFET in under 5nm manufacturing is something that many industry analysts and specialist thought extremely difficult to achieve, with expectations for these sub-5nm nodes to require more exotic materials and transistor designs than TSMC's apparent plans

AMD's 7 nm "Renoir" silicon breathed life into the notebook processor market, by bringing 8-core/16-thread CPU performance into segments Intel reserved for 4-core/8-thread; and beat Intel in the iGPU performance front. 7 nm brought performance-Watt uplifts that spell serious competition for Intel across all notebook form factors, be it 15 W or 45 W. According to _rogame, who has a knack of getting far-out hardware rumors right, AMD has its successor on the drawing-board, and it's codenamed "Cézanne," after the French post-impressionist painter Paul Cézanne.

"Cézanne" could prove vital for AMD's foothold in the premium mobile computing segments as Intel is preparing to launch its 10 nm+ "Tiger Lake" processor soon, with advanced "Willow Cove" CPU cores, and Xe based integrated graphics. AMD plans to tap into its very latest IP. Although its core-count is not known, "Cézanne" will feature CPU cores based on the latest "Zen 3" microarchitecture. The iGPU will receive its biggest performance uplift in 3 generations, with an iGPU based on the cutting-edge RDNA2 graphics architecture that meets DirectX 12 Ultimate logo requirements.

According to the report of DigiTimes, which talked about TSMC's 5 nm silicon manufacturing node, they have reported that NVIDIA is also going to be a customer for it and they could use it in the near future. And that is very interesting information, knowing that these chips will not go in the next generation of GPUs. Why is that? Because we know that NVIDIA will utilize both TSMC and Samsung for their 7 nm manufacturing nodes for its next-generation Ampere GPUs that will end up in designs like GeForce RTX 3070 and RTX 3080 graphics cards. These designs are not what NVIDIA needs 5 nm for.

Being that NVIDIA already has a product in its pipeline that will satisfy the demand for the high-performance graphics market, maybe they are planning something that will end up being a surprise to everyone. No one knows what it is, however, the speculation (which you should take with a huge grain of salt) would be that NVIDIA is updating its Tegra SoC with the latest node. That Tegra SoC could be used in a range of mobile devices, like the Nintendo Switch, so could NVIDIA be preparing a new chip for Nintendo Switch 2?

While AMD's 7 nm "Renoir" APU silicon is off busy disrupting the mobile processor market, AMD needs a socket AM4 desktop APU to challenge Intel's Core i5 and Core i7 chips that have iGPUs, and it's only natural for "Renoir" to reach the desktop platform at some point. PC enthusiast _rogame unearthed details of a 35-Watt TDP AMD APU codenamed "Artic," with a rather high 3.00 GHz nominal clock speed, which could hint at the possibility of this being a desktop part. The part in question also features an iGPU ticking at 1200 MHz, and DDR4-3200 memory.

AMD has released Renoir on the mobile platform at 15 W and 45 W power-envelopes. It has, in the past, similarly segmented its desktop APUs into 65 W and energy-efficient 35 W TDP parts, with the latter using lower clock speeds and aggressive power-management to hold on to its TDP. This chip could be the latter, a possible "Ryzen 3 4200GE" of sorts. _rogame mentions that the iGPU performance is a notch lower than the 6 CU "Renoir" parts such as the 4600H, while the CPU performance is higher than the 8-core/8-thread 4700U. Here's hoping we find out more soon.

Intel's first integrated graphics solution based on its ambitious new Xe graphics architecture, could match AMD's "Vega" architecture based iGPU solutions, such as the one found in its latest Ryzen 4000 series "Renoir" iGPUs, according to leaked 3DMark FireStrike numbers put out by @_rogame. Benchmark results of a prototype laptop based on Intel's "Tiger Lake-U" processor surfaced on the 3DMark database. This processor embeds Intel's Gen12 Xe iGPU solution, which is purported to offer significant performance gains over current Gen11 and Gen9.5 based iGPUs.

The prototype 2-core/4-thread "Tiger Lake-U" processor with Gen12 graphics yields a 3DMark FireStrike score of 2,196 points, with a graphics score of 2,467, and 6,488 points physics score. These scores are comparable to 8 CU Radeon Vega iGPU solutions. "Renoir" tops out at 8 CUs, but shores up performance to the 11 CU "Picasso" levels by other means. Besides tapping into the 7 nm process to increase engine clocks, improve the boosting algorithm, and modernizing the display- and multimedia engines; AMD's iGPU is largely based on the same 3-year old "Vega" architecture. Intel Gen12 Xe makes its debut with the "Tiger Lake" microarchitecture slated for 2021.

With an introduction of new iPad Pro tablets, Apple has brought another new silicon to its offerings in the form of A12Z SoC. Following the previous king in tablet space, the A12X SoC, Apple has decided to update its silicon and now there is another, more advanced stepping in form of an A12Z SoC. Thanks to the report from TechInsights, their analysis has shown that the new SoC used in Apple's devices is pretty much the same compared to the A12X SoC of last year, except the GPU used. Namely, the configuration of A12X is translated into the A12Z - there are four Apple Vortex and four Apple Tempest cores for the CPU. There is a 128-bit memory bus designed for LPDDR4X memory, the same as the A12X.

What is different, however, is the GPU cluster configuration. In A12X there was a cluster filled with 7 working and one disabled A12-gen GPU core. In A12Z SoC all of the 8 GPUs present are enabled and working, and they are also of the same A12 generation. The new SoC is even built using the same N7 7 nm manufacturing process from TSMC. While we don't know the silicon stepping revision of the A12Z, there aren't any new features besides the additional GPU core.

Huawei's subsidiary, HiSilicon, which designs the processors used in Huawei's smartphones and telecommunications equipment, has reportedly moved its silicon orders from Taiwan Semiconductor Manufacturing Company (TSMC) to Semiconductor Manufacturing International Corporation (SMIC), according to DigiTimes. Why Huawei decided to do is move all of the 14 nm orders from Taiwanese foundry to China's largest silicon manufacturing fab, is to give itself peace of mind if the plan of the US Government goes through to stop TSMC from supplying Huawei. At least for the mid-tier chips built using 14 nm node, Huawei would gain some peace as a Chinese fab is a safer choice given the current political situation.

When it comes to the high-end SoCs built on 7 nm, and 5 nm in the future, it is is still uncertain how will Huawei behave in this situation, meaning that if US cuts off TSMC's supply to Huawei, they will be forced to use SMIC's 7 nm-class N+1 node instead of anything from TSMC. Another option would be Samsung, but it is a question will Huawei put itself in risk to be dependant on another foreign company. The lack of 14 nm orders from Huawei will not be reflecting much on TSMC, because whenever someone decides to cut orders, another company takes up the manufacturing capactiy. For example, when Huawei cut its 5 nm orders, Apple absorbed by ordering more capacity. When Huawei also cut 7 nm orders, AMD and other big customers decided to order more, making the situation feel like there is a real fight for TSMC's capacity.

Samsung is determined in its plans to deliver the 3 nm silicon manufacturing process in the year 2022, and with it, there will be some major improvements to the transistor technology. We have already mentioned that Samsung is working on Gate-All-Around FET technology that will bring much better control of the transistor channel, preventing leakage at smaller nodes. However, today Samsung added a few more details about its upcoming Multi Bridge Channel FET technology for a 3 nm manufacturing process, simply called the MBCFET. Thanks to the report from Hardwareluxx, we have more details regarding the MBCFET technology and its characteristics.

Firstly, it is worth noting that MCBFET is a part of GAAFETs, meaning that the GAAFET is not one product, but rather a class of many based on its concepts. As far as the MCBFET performance goes, Samsung says that the technology will use 50% less power while delivering 30% more performance. There is going to be a big density gain as well, where Samsung predicts there will be around 45% less silicon space taken per one transistor. The comparison is made to an unspecified 7 nm process, possibly Samsung's process that uses FinFETs. The technology allows the stacking of transistors on top of each other, which makes it use inherently less space compared to regular FinFET. Being that MCBFET GAA transistors make its transistor width flexible, it means that the overall stacked transistor can be as wide as a designer needs it to be, adjusting for any scenario like low-power or high-performance.

AMD's 4th generation Ryzen desktop processors are expected to launch around September 2020, sources in the motherboard industry tell DigiTimes. Codenamed "Vermeer," successor to "Matisse," these processors will be socket AM4 multi-chip modules of up to two CPU complex dies based on the "Zen 3" microarchitecture, combined with an I/O controller die. The "Zen 3" chiplets are expected to be fabricated on a newer 7 nm-class process by TSMC, either N7P or N7+. The biggest design change with "Zen 3" is the doing away of CCX arrangement of CPU cores, with each chiplet holding a common block of cores sharing a last-level cache. This, along with clock speed headroom gains from the new node are expected to yield generational price-performance increases.

The "Zen 2" based 8-core "Renoir" die is also expected to make its socket AM4 debut within 2020, succeeding the "Picasso" based quad-core Ryzen 3000-series APUs. This is a particularly important product for AMD, as it is expected to compete with Intel's 10th generation Core i5 6-core/12-thread processors in terms of pricing, while offering more cores (8-core/16-thread) and a faster iGPU. The 4th gen Ryzen socket AM4 processor lineup will launch alongside AMD's 600-series motherboard chipset, with forwards- and backwards-compatibility (i.e., "Vermeer" and "Renoir" working with older chipsets, and older AM4 processors working on 600-series chipset motherboards). AMD was originally expected to unveil these processors at the 2020 Computex trade-show in June, but Computex itself is rescheduled to late-September.

China's state-backed SMIC (Semiconductor Manufacturing International Corporation) has set an ambitious target of Q4-2020 for its 7 nanometer-class N+1 foundry node to go live, achieving "small scale production," according to a cnTechPost report. The company has a lot of weight on its shoulders as geopolitical hostility between the U.S. and China threatens to derail the country's plans to dominate 5G technology markets around the world. The SMIC N+1 node is designed to improve performance by 20%, reduce chip power consumption by 57%, reduce logic area by 63%, and reduce SoC area by 55%, in comparison to the SMIC's 14 nm FinFET node, Chinese press reports citing a statement from SMIC's co-CEO Dr. Liang Mengsong.

Dr. Liang confirmed that the N+1 7 nm node and its immediate successor will not use EUV lithography. N+1 will receive a refinement in the form of N+2, with modest chip power consumption improvement goals compared to N+1. This is similar to SMIC's 12 nm FinFET node being a refinement of its 14 nm FinFET node. Later down its lifecycle, once the company has got a handle of its EUV lithography equipment, N+2 could receive various photomasks, including a switch to EUV at scale.

Cadence, a fabless semiconductor company focusing on the development of IP solutions and IC design and verification tools, today posted an update regarding their development efforts for the 5th generation of DDR memory which is giving us some insights into the development of a new standard. The new DDR5 standard is supposed to bring better speeds and lower voltages while being more power-efficient. In the Cadence's blog called Breakfast Bytes, one of Cadence's memory experts talked about developments of the new standards and how they are developing the IP for the upcoming SoC solutions. Even though JEDEC, a company developing memory standards, hasn't officially published DDR5 standard specifications, Cadence is working closely with them to ensure that they stay on track and be the first on the market to deliver IP for the new standard.

Marc Greenberg, a Cadence expert for memory solutions was sharing his thoughts in the blog about the DDR5 and how it is progressing. Firstly, he notes that DDR5 is going to feature 4800 MT/s speeds at first. The initial speeds will improve throughout the 12 months when the data transfer rate will increase in the same fashion we have seen with previous generation DDR standards. Mr. Greenberg also shared that the goals of DDR5 are to have larger memory dies while managing latency challenges, same speed DRAM core as DDR4 with a higher speed I/O. He also noted that the goal of the new standard is not the bandwidth, but rather capacity - there should be 24Gb of memory per die initially, while later it should go up to 32Gb. That will allow for 256 GB DIMMs, where each byte can be accessed under 100 ns, making for a very responsive system. Mr. Greenberg also added that this is the year of DDR5, as Cadence is receiving a lot of orders for their 7 nm IP which should go in production systems this year.

The U.S. government announced advanced measures that make it harder for foreign companies, such as Taiwan's TSMC, to supply chips to Chinese telecom hardware giant Huawei. Foreign companies that use American chipmaking equipment, are required to obtain a license from the U.S. before supplying certain chips to Huawei. Sources comment that the new rule was tailor-made to curb TSMC fabricating smartphone SoCs for Huawei's HiSilicon subsidiary.

Mainland Chinese semiconductor companies are still behind Samsung and TSMC in 7 nm-class fab technologies, forcing HiSilicon to source from the latter. 7 nm fabrication is a key requirement for SoCs and modem chips capable of 5G. The high data transceiving rates of 5G requires a certain amount of compute power that can fit into smartphone-level power-envelopes only with the help of 7 nm, at least for premium smartphone form-factors. Same applies to 5G infrastructure equipment. This is hence perceived as a means for the U.S. to clamp brakes on Huawei's plans of playing a big role in 5G tech rollouts around the world, buying western 5G tech suppliers such as Nokia time to catch up. Huawei has been a flashpoint for a bitter political spat between the U.S. and China, with the Chinese press even threatening that the matter could hamper medical supplies to the U.S. to fight the COVID-19 pandemic.

A WikiChip analysis of TSMC's next-generation 5 nanometer N5P silicon fabrication node estimates a massive 84-87% increase in transistor densities on offer compared to the company's first commercial 7 nm-class node, the N7 (7 nm DUV). The report estimates an 87% transistor-density increase, even though TSMC's own figure is slightly modest, at 84%. TSMC N5P node is expected to commence production later this year. Its precursor, TSMC N5, began risk production earlier this year, with production on the node commencing in April or May, unless derailed by the COVID-19 pandemic. The N5P node provides transistor densities of an estimated 171.3 million transistors per mm² die area, compared to 91.2 mTr/mm² of N7. Apple is expected to be the node's biggest customer in 2020, with the company building its A14-series SoC on it.

Sony in a YouTube stream keynote by PlayStation 5 lead system architect Mark Cerny, detailed the upcoming entertainment system's hardware. There are three key areas where the company has invested heavily in driving forward the platform by "balancing revolutionary and evolutionary" technologies. A key design focus with PlayStation 5 is storage. Cerny elaborated on how past generations of the PlayStation guided game developers' art direction as the low bandwidths and latencies of optical discs and HDDs posed crippling latencies arising out of mechanical seeks, resulting in infinitesimally lower data transfer rates than what the media is capable of in best case scenario (seeking a block of data from its outermost sectors). SSD was the #1 most requested hardware feature by game developers during the development of PS5, and Sony responded with something special.

Each PlayStation 5 ships with a PCI-Express 4.0 x4 SSD with a flash controller that has been designed in-house by Sony. The controller features 12 flash channels, and is capable of at least 5.5 GB/s transfer speeds. When you factor in the exponential gains in access time, Sony expects the SSD to provide a 100x boost in effective storage sub-system performance, resulting in practically no load times.

Here is the first die visualization of AMD's new "Renoir" processor. Having made its debut with Ryzen 4000 series mobile processors, "Renoir" succeeds a decade-long legacy of AMD APUs that combine CPUs with powerful iGPUs. AMD designed "Renoir" on TSMC's 7 nm silicon fabrication process. The die measures 156 mm², and has a transistor-count of 9.8 billion. The die shot reveals distinct areas that look like the processor's 8 CPU cores, a cluster of GPU compute units, the integrated memory controllers, southbridge, and PHYs for the chip's various I/O.

"Renoir" features 8 CPU cores based on the "Zen 2" microarchitecture, divided into two 4-core CCXs (CPU complexes). Unlike on 8-core chiplets meant for "Matisse" or "Rome" MCMs, the "Renoir" CCX only features 4 MB of shared L3 cache, probably because latencies to the memory controller are low enough. The L2 cache per core is unchanged at 512 KB. The "total cache" (L2 + L3 on silicon) adds up to 12 MB. The iGPU of "Renoir" is a hybrid between "Vega" and "Navi." The SIMD components are carried over from "Vega," while the display- and multimedia engines are from "Navi." The iGPU features 8 NGCUs that add up to 512 stream processors. Infinity Fabric covers much of the die area, connecting the various components on the die. AMD introduced a new dual-channel integrated memory controller that supports LPDDR4x at up to 4233 MHz, and standard DDR4 up to 3200 MHz.

Microsoft just put out of the complete hardware specs-sheet of its next-generation Xbox Series X entertainment system. The list of hardware can go toe to toe with any modern gaming desktop, and even at its production scale, we're not sure if Microsoft can break-even at around $500, possibly counting on game and DLC sales to recover some of the costs and turn a profit. To begin with the semi-custom SoC at the heart of the beast, Microsoft partnered with AMD to deploy its current-generation "Zen 2" x86-64 CPU cores. Microsoft confirmed that the SoC will be built on the 7 nm "enhanced" process (very likely TSMC N7P). Its die-size is 360.45 mm².

The chip packs 8 "Zen 2" cores, with SMT enabling 16 logical processors, a humongous step up from the 8-core "Jaguar enhanced" CPU driving the Xbox One X. CPU clock speeds are somewhat vague. It points to 3.80 GHz nominal and 3.66 GHz with SMT enabled. Perhaps the console can toggle SMT somehow (possibly depending on whether a game requests it). There's no word on the CPU's cache sizes.

Microsoft's upcoming Xbox Series X entertainment system is shaping up to be a technological monstrosity. Xbox group head at Microsoft, Phil Spencer, last revealed a picture of its semi-custom SoC back in January, by setting it as his Twitter display picture. Over the following weeks, many more technical details, such as the chip's 12 TFLOP/s combined compute power, would be let out. Spencer updated his display picture revealing a segment of the Xbox Series X mainboard with the SoC and memory chips surrounding it. The picture reveals the large SoC package in the center, surrounded on three sides by ten memory chips, possibly GDDR6, each with its own wiring to the SoC. This indicates that the SoC features a 320-bit wide memory interface.

As for the memory density, there's no way to tell. It could be 10 GB if those are 8 Gbit memory chips, or 20 GB if those are 16 Gbit. It boils down to which device the Xbox Series X the company wants to succeed. The Xbox One S features 8 GB of DDR3, while the spruced up Xbox One X features 12 GB of GDDR5. If the new Xbox Series X succeeds the latter, then it could very well feature 20 GB, more so given Microsoft's lofty design goals (4K UHD gaming with real-time ray-tracing). Microsoft leverages hUMA to use a common memory pool for both the CPU and GPU. Designed in collaboration with AMD on a TSMC 7 nm-class node (likely the N7P), the SoC features "Zen 2" CPU cores, and a GPU based on the RDNA2 graphics architecture.