Monday, December 11th 2023
Intel Demos 3D Transistors, RibbonFET, and PowerVia Technologies
During the 69th annual IEEE International Electron Devices Meeting (IEDM), Intel demonstrated some of its latest transistor design and manufacturing advancements. The first one in line is the 3D integration of transistors. According to Intel, the company has successfully stacked complementary field effect transistors (CFET) at a scaled gate pitch down to 60 nm. With CFETs promising thinner gate channels, the 3D stacked CFET would allow for higher density by going vertically and horizontally. Intel's 7 node has a 54 nm gate pitch, meaning CFETs are already close to matching production-ready nodes. With more time and development, we expect to see 3D stacked CFETs in the production runs in the coming years.
Next, Intel has demonstrated RibbonFET technology, a novel approach that is the first new transistor architecture since the introduction of FinFET in 2012. Using ribbon-shaped channels surrounded by the gate, these transistors allow for better control and higher drive current at all voltage levels. This allows faster transistor switching speeds, which later lead to higher frequency and performance. The width of these nanoribbon channels can be modulated depending on the application, where low-power mobile applications use less current, making the channels thinner, and high-performance applications require more current, making the channels wider. One stack of nanoribbons can achieve the same drive current as multiple fins found in FinFET but at a smaller footprint.Next up, we learn that Intel has commented that its PowerVia technology is production-ready, with the first products utilizing PowerVia expected to arrive in 2024. PowerVia is Intel's efforts to change the structure of the transistor power delivery, moving the power routing wires from the top to below the transistor in an effort to manage power efficiently and not obscure signal wires found on the top of the transistor. PowerVia is formed into a backside power delivery network that operates without contact with the single network in the chip. The connection to the transistor layer is made using nano through silicon vias (TSVs), which are 500 times smaller than regular TSVs.Intel has also demonstrated the integration of silicon and GaN. The company successfully established a high-performance, large-scale integrated circuit solution called "DrGaN" for power delivery. This solution can potentially enable power delivery solutions to keep pace with the power density and efficiency demands of future computing. Additionally, the company will also present transition metal dichalcogenide (TMD) 2D channel materials, which offer a scaling path for transistor physical gate length below 10 nm. Intel is scheduled to demonstrate prototypes of the CMOS design's high-mobility TMD transistors for NMOS (n-channel metal oxide semiconductor) and PMOS (p-channel metal oxide semiconductor) elements. Lastly, the company will also present the so-claimed world's first gate-all-around (GAA) 2D TMD PMOS transistor and the world's first 2D PMOS transistor fabricated on a 300 mm wafer, all dedicated to scaling transistor density further.
Sources:
Intel, Intel (YouTube Video)
Next, Intel has demonstrated RibbonFET technology, a novel approach that is the first new transistor architecture since the introduction of FinFET in 2012. Using ribbon-shaped channels surrounded by the gate, these transistors allow for better control and higher drive current at all voltage levels. This allows faster transistor switching speeds, which later lead to higher frequency and performance. The width of these nanoribbon channels can be modulated depending on the application, where low-power mobile applications use less current, making the channels thinner, and high-performance applications require more current, making the channels wider. One stack of nanoribbons can achieve the same drive current as multiple fins found in FinFET but at a smaller footprint.Next up, we learn that Intel has commented that its PowerVia technology is production-ready, with the first products utilizing PowerVia expected to arrive in 2024. PowerVia is Intel's efforts to change the structure of the transistor power delivery, moving the power routing wires from the top to below the transistor in an effort to manage power efficiently and not obscure signal wires found on the top of the transistor. PowerVia is formed into a backside power delivery network that operates without contact with the single network in the chip. The connection to the transistor layer is made using nano through silicon vias (TSVs), which are 500 times smaller than regular TSVs.Intel has also demonstrated the integration of silicon and GaN. The company successfully established a high-performance, large-scale integrated circuit solution called "DrGaN" for power delivery. This solution can potentially enable power delivery solutions to keep pace with the power density and efficiency demands of future computing. Additionally, the company will also present transition metal dichalcogenide (TMD) 2D channel materials, which offer a scaling path for transistor physical gate length below 10 nm. Intel is scheduled to demonstrate prototypes of the CMOS design's high-mobility TMD transistors for NMOS (n-channel metal oxide semiconductor) and PMOS (p-channel metal oxide semiconductor) elements. Lastly, the company will also present the so-claimed world's first gate-all-around (GAA) 2D TMD PMOS transistor and the world's first 2D PMOS transistor fabricated on a 300 mm wafer, all dedicated to scaling transistor density further.
57 Comments on Intel Demos 3D Transistors, RibbonFET, and PowerVia Technologies
At least that is how I see it.
And if they didn't make compromises with heterogenous cores (e.g. cutting AVX-512) as an attempt to overcome that inefficiency... but they did.
Do most end-users understand this or care? No. But as a technology enthusiast, I do. And in terms of technological innovation, Intel's CPUs are pathetic rubbish that are just compromises built on top of compromises built on top of an architecture that has been around for many generations too long.
I also agree on the heterogenous cores, which is a perfectly sound idea for mobile, but a red flag on desktop for many users, myself included (mainly due to the need to use Windows 11's scheduler).
My version of the story.
The distrust in heterogenous architectures on desktop is a me-thing. I don't want to use Spydows 11 just to utilise my CPU properly, that's all.
Ultimately I do believe that heterogenous cores are the inevitable future on desktop and mobile - and Intel's investment into them may well put it ahead in the long term. But right now, they're just an inferior crutch; the right solution to the wrong problem.
I dont have distrust but rather I have doubts it is that much better. Oh that is so true.
But you also want to look for a way out from a check (chess analogy) the best way you can.
The next question is, is AMD going to do the same thing? What if they do?
Maybe if Intel's e-cores were more like AMD's dense cores and were logically the same to the OS and offered SMT it would be different but they don't even yield great battery life in mobile. Now Intel have low powered E cores to further complicate things.
I'm all in on Intel's tile approach and it's far more advanced than AMD's chiplets at the moment, who will no doubt be moving to something similar down the track. Maybe MTL won't be impressive, but you start somewhere and each gen will surely improve. I would never ever buy into a brand new first gen architecture on principle, but I do eagerly await Arrow Lake, and Panther Lake.
Nothing is objectively bad unless it explodes and sets your house on fire, or at least isn't working. :)
For example, if the price and power consumption is a little bit on the high side, but the performance is excellent, that makes a good enough CPU, in my opinion. Unfortunately, this is not the case with 12th-14th gen Intel i7 and i9, as while the performance is there, and the price isn't too bad, power consumption, and thus, heat, is through the roof. The three values you listed each have a certain threshold above/below which the other two characteristics can't help anymore.
As long as you can cool the CPU, what does it matter. People seem to forget that both AMD and Intel design their CPU's to run at their max temp 100c for example, all day with no problems.