Thursday, October 5th 2023
Samsung and TSMC Reportedly Struggling with 3 nm Yields
According to Korean business news publication ChosunBiz, both Samsung and TSMC are struggling with their 3 nm node yields. The two companies have different approaches to their 3 nm nodes, with Samsung using GAA FET (Gate All Around), whereas TSMC is continuing with its FinFET technology. That said, TSMC has at least five known 3 nm nodes, of which two should be in production by now, assuming N3E has proved to be reliable enough to kick off. Samsung on the other hand has three known 3 nm nodes, with only one in production so far, called 3GAE.
ChosunBiz reports that neither company is getting the kind of yields that you'd expect from a node that should have been in volume production for around a year by now, with Samsung apparently being somewhat better than TSMC. At 60 and 50 percent respectively, neither Samsung nor TSMC are anywhere near decent yields. Anything below 70 percent is considered very poor and even the 60 percent claim in Samsungs case, is apparently limited to some kind of Chinese mining ASIC and doesn't include the SRAM you find in most modern processors. ChosunBiz also mentions a source familiar with Samsung's foundry business who mentions a yield closer to 50 percent for the company. The same source also mentions that Samsung needs to reach at least 70 percent yield to be able to attract major customers to its 3 nm node.
Sources:
ChosunBiz, via @Tech_Reve (on X)
ChosunBiz reports that neither company is getting the kind of yields that you'd expect from a node that should have been in volume production for around a year by now, with Samsung apparently being somewhat better than TSMC. At 60 and 50 percent respectively, neither Samsung nor TSMC are anywhere near decent yields. Anything below 70 percent is considered very poor and even the 60 percent claim in Samsungs case, is apparently limited to some kind of Chinese mining ASIC and doesn't include the SRAM you find in most modern processors. ChosunBiz also mentions a source familiar with Samsung's foundry business who mentions a yield closer to 50 percent for the company. The same source also mentions that Samsung needs to reach at least 70 percent yield to be able to attract major customers to its 3 nm node.
81 Comments on Samsung and TSMC Reportedly Struggling with 3 nm Yields
It's a bad business strategy and they haven't done so poorly in a very long time.
You keep ignoring the real customers, server farms. None of those people want big node chips.
Like I said, 11% share of their declining revenue is a band aid to stop the bleeding, it isnt success by any measure.
Don't even get me started on the covid excuse, like every single chip company didnt deal with that and make record profits, which intel didnt funnel into innovating cpus, they chose to make gpus instead.
3 CEO's in the past 5 years spells it all out. I can recognize a dumpster fire when I see one, no leadership at all, peoplewith insider knowledge jumping ship... Sounds like twitter, unity, meta, twitch, you pick.
Because Intel 4 is not in mass production while TSMC N5 has been in mass production for 2 years.
I can't explain enough how much fun it is to watch a large group of media outlets, bought-out by money, continue to spread disinformation while Intel continues to drop competitive product.
Two years ago:
From: arstechnica.com/gadgets/2021/07/intels-foundry-roadmap-lays-out-the-post-nanometer-angstrom-era/:
"Gone are the days of "Intel 10nm Enhanced Super Fin"—instead, the node is called "Intel 7." It should have a comparable density to the TSMC and Samsung 7 nm nodes and will be ready for production in Q1 2022 (TSMC and Samsung are currently shipping "5nm" products). "Intel 4"—which Intel previously called "7nm"—is now said to be equivalent to TSMC and Samsung's 4 nm node, and it will begin manufacturing products in 2023."
Two years later... Play it again tech bros! It must be working by now.. ;)
What happened to overclockers.com? Where's Tom? Where's Anand?
*winks*
I think intel chose to lie and mislead.
www.semiaccurate.com/2021/04/07/intel-should-not-rename-their-processes/Yes, that's why Apple and the others can ask for lower wafers prices because of the terrible yields !
Did you read the article that you linked to me? ? the author is saying that everyone in the game is being dishonest, and Intel renaming will just prompt the other foundries to rename their process just for the sake of making Intel looks bad.
As for Intel... fool me once, shame on you; fool me twice, shame on recycling 14nm for half a decade.
TSMC Said to Start Construction of 1.4 nm Fab in 2026 | TechPowerUp
Samsung Updates Foundry Roadmap: 2nm in 2025, 1.4nm in 2027 (anandtech.com)
Angstrom Definition & Meaning - Merriam-Webster
For example, N7, N5, N4, N3, N2.
I told you N7 =/ 7 nm :D
Also, intel's "20A" is around TSMC N5, not around TSMC N2.. and definitely not 2.0 nm...
5nm Technology - Taiwan Semiconductor Manufacturing Company Limited (tsmc.com)
What I am arguing is that intel lies, it can call its next process "process 0" and call it a day, forever. Won't change the fact that it will be the same process as its 10nm/intel 7.
So what Intel is doing is not worse than what the other are doing. They are playing the same game. Intel 7 nm is twice a dense as TSMC 7nm (N7), it's a full generation better than the 7nm of everybody else, and actually meant to compete with the 5nm of everybody else. Intel is adjusting to the fact that TSMC node nomenclature is what the industry revolves around now. Intel keeping their old naming scheme would do nothing besides having the occasional troll laughing at how their numbers are always behind TSMC even if they manage to catch up.
Intel having a "nm" parity with everybody else would actually mean that they would have a full generational advantage:
Yes, it's a pure marketing ploy, but you don't buy a CPU based on its nm. You look at reviews and then you make your decision. And Intel fabs clients are savvy enough to know what's up. It's not like they will try and sell an old process as a bleeding edge node. The die size of a prototype alone will show that something isn't right. nm might have lost their original meaning, but you can't cheat density.
I feel like some people here think that Alder Lake and Raptor Lake not being as efficient as AMD CPUs is a proof that intel 10nm is in fact a TSMC 10 nm...It's not the case, the architecture is just not as efficient. Do people need a reminder about maxwell being much more efficient than GCN on the same node? Or the zen 2 to zen 3 improvements on the same node?
AMD Ryzen 9 5900X Review - Power Consumption & Efficiency | TechPowerUp
NVIDIA GeForce GTX 980 4 GB Review - Power Consumption | TechPowerUp
This means that a high-density N5 chip can be more dense than a low-density N3 chip.
And here the idea - instead of a race to 0 "nm", call the "processes" according to the achievable or achieved transistor density/transistor count. It will be better.
For instance: TSMC 200, TSMC 150, TSMC 100, where the higher the number, the better.
Here's an article by David Kanter I often recommend, it has many details regarding this same topic, however as an EE with no background in microelectronics, it's not an easy read.
www.realworldtech.com/transistor-count-flawed-metric/
***
And here's one issue I'm wondering about, and can't find an answer: CPUS and other types of processors have significant parts of the die dedicated to cache (static RAM). If there's a couple defects in the L2 or L3 area, does that mean that the entire core or an entire L3 slice is unusable - or can just a few cache lines be marked as bad, while the other 99.9% are still operational? The latter would certainly enable much better yields.