Wednesday, July 24th 2024
CPU-Z Screenshot of Alleged Intel Core Ultra 9 285K "Arrow Lake" ES Surfaces, Confirms Intel 4 Process
A CPU-Z screenshot of an alleged Intel Core Ultra 9 285K "Arrow Lake-S" desktop processor engineering sample is doing rounds on social media, thanks to wxnod. CPU-Z identifies the chip with an Intel Core Ultra case badge with the deep shade of blue associated with the Core Ultra 9 brand extension, which hints at this being the top Core Ultra 9 285K processor model, we know it's the "K" or "KF" SKU looking at its processor base power reading of 125 W. The chip is built in the upcoming Intel Socket LGA1851. CPU-Z displays the process node as 7 nm, which corresponds with the Intel 4 foundry node.
Intel is using the same Intel 4 foundry node for "Arrow Lake-S" as the compute tile of its "Meteor Lake" processor. Intel 4 offers power efficiency and performance comparable to 4 nm nodes from TSMC, although it is physically a 7 nm node. Likewise, the Intel 3 node is physically 5 nm. If you recall, the main logic tile of "Lunar Lake" is being built on the TSMC N3P (3 nm) node. This means that Intel is really gunning for performance/Watt with "Lunar Lake," to get as close to the Apple M3 Pro as possible.
"Arrow Lake" features the same "Lion Cove" P-cores and "Skymont" E-cores as "Lunar Lake," but connected differently. In "Lunar Lake," the P-core complex sits on its own tiny ringbus with an exclusive L3 cache; with the E-core clusters being separated into low-power islands. The two core types talk to each other over the chip's high bandwidth fabric. In "Arrow Lake," however, the "Lion Cove" P-cores and "Skymont" E-core clusters share a ringbus and L3 cache, like the two core types do on current "Raptor Lake" chips. Intel will innovate with the way the P-cores and E-core clusters are physically arranged along the ringbus, and you can read all about it in our older article.
Back to the CPU-Z screenshot, and we're shown a clock speed of 5.00 GHz. This is likely being read off the first "Lion Cove" P-core. The P-cores have 48 KB of L1 Data (L1D) and 64 KB of L1 Instructions (L1I) caches; while the E-cores have 32 KB of L1D and 64 KB of L1I caches. We've known since the "Lunar Lake" technical deep-dive from Intel's comments, that the "Lion Cove" P-cores on "Arrow Lake" will get 3 MB of dedicated L2 caches, compared to 2.5 MB per core on "Lunar Lake." Each of the four "Skymont" E-core clusters of "Arrow Lake" shares 4 MB of L2 cache among the four cores in the cluster.
The total L2 cache on "Arrow Lake-S" is 40 MB. This is from eight 3 MB caches from the P-cores, and four 4 MB caches from the E-core clusters (24 MB + 16 MB). We are now learning that the shared L3 cache size remains 36 MB on "Arrow Lake."
Since the "Lion Cove" P-cores lack HyperThreading, "Arrow Lake-S" is a 24-core/24-thread processor. The generational performance gain over the current Core i9-14900K will boil down to the ~14% IPC gain of "Lion Cove" over "Redwood Cove" (which in-turn was within 2% of "Raptor Cove"); and the massive 38-68% IPC improvement of the "Skymont" E-core over the "Crestmont" E-core (which in turn was +8% over "Gracemont.").
Intel is expected to debut the Core Ultra 200 series "Arrow Lake-S" desktop processors, and the LGA1851 platform led by the Intel Z890 chipset, around late-September or early-October, 2024.
Sources:
wxnod (Twitter), HXL (Twitter)
Intel is using the same Intel 4 foundry node for "Arrow Lake-S" as the compute tile of its "Meteor Lake" processor. Intel 4 offers power efficiency and performance comparable to 4 nm nodes from TSMC, although it is physically a 7 nm node. Likewise, the Intel 3 node is physically 5 nm. If you recall, the main logic tile of "Lunar Lake" is being built on the TSMC N3P (3 nm) node. This means that Intel is really gunning for performance/Watt with "Lunar Lake," to get as close to the Apple M3 Pro as possible.
Back to the CPU-Z screenshot, and we're shown a clock speed of 5.00 GHz. This is likely being read off the first "Lion Cove" P-core. The P-cores have 48 KB of L1 Data (L1D) and 64 KB of L1 Instructions (L1I) caches; while the E-cores have 32 KB of L1D and 64 KB of L1I caches. We've known since the "Lunar Lake" technical deep-dive from Intel's comments, that the "Lion Cove" P-cores on "Arrow Lake" will get 3 MB of dedicated L2 caches, compared to 2.5 MB per core on "Lunar Lake." Each of the four "Skymont" E-core clusters of "Arrow Lake" shares 4 MB of L2 cache among the four cores in the cluster.
The total L2 cache on "Arrow Lake-S" is 40 MB. This is from eight 3 MB caches from the P-cores, and four 4 MB caches from the E-core clusters (24 MB + 16 MB). We are now learning that the shared L3 cache size remains 36 MB on "Arrow Lake."
Since the "Lion Cove" P-cores lack HyperThreading, "Arrow Lake-S" is a 24-core/24-thread processor. The generational performance gain over the current Core i9-14900K will boil down to the ~14% IPC gain of "Lion Cove" over "Redwood Cove" (which in-turn was within 2% of "Raptor Cove"); and the massive 38-68% IPC improvement of the "Skymont" E-core over the "Crestmont" E-core (which in turn was +8% over "Gracemont.").
Intel is expected to debut the Core Ultra 200 series "Arrow Lake-S" desktop processors, and the LGA1851 platform led by the Intel Z890 chipset, around late-September or early-October, 2024.
57 Comments on CPU-Z Screenshot of Alleged Intel Core Ultra 9 285K "Arrow Lake" ES Surfaces, Confirms Intel 4 Process
Ok it's for AMD just in case it wasn't clear!
Set it to a 12 out of 10 chances of burning without dry ice, delid, and liquid metal as the out of box experience.
Hell, even release day hardware can have updates waiting that SIGNIFICANTLY improves performance or fixes a performance bug - most new motherboard/chipset BIOS updates are usually this exact thing rather than feature improvements. Can't imagine how bad / flakey some of this stuff must be before it's even finished widespread / OEM validation work.
The likelihood is that screenshot will have been taken on a device which is still actually buggy somewhere...
This is why early adopters are called guinea pigs.
And it makes no sense to skip a fully grown intel 4 (7nm) node just like that when 14nm has been in use for almost a decade.
To be honest, AMD actually released AM5 with some fairly high DDR5 speeds out of the box and mandating certain speeds for RAM testing. I bet if they said "hey just aim to use DDR5-4800 / 5200" there would have been a lot less issues with boards / RAM makers - they literally put themselves in a situation where everybody was in the mindset of DDR5-6000 or bust.
When Intel released the X99 platform, it was pretty much DDR4-2133 or 2400 as their pitch - sure companies like Asus were like "shoot for 3200" and many of the CPUs could make that happen but it wasn't the main company line from Intel.
Staying on topic, we have no idea what the parameters around the leaked screenshots are. Seeing as potentially less than 6 months from release, hopefully most of the BIOS/support software is out of the Alpha stages and in Beta/RC stages. For sure, OEM sampling must be going on and of course is the source for these leaks really.
I was originally planning to upgrade to a 13400F coming from a 12100F but for some reason the 12600KF was like 30$ cheaper so I was like alright I will bite cause even at stock its still a faster CPU for cheaper. 'I've undervolted it and this way its actually decently efficient and cool'
Since the very late 2000s most of the handheld market SoCs had moved to a memory on CPU stacked design - it offered economy of space and packaging, but of course with higher speeds now it also offers the chance to have higher clock speeds due to ultra short signal paths. PC makers have opted to instead go with LPDDR configurations as it means keeping the same core dies they use elsewhere for the most part, but even Intel is moving to a mix with their new laptop SoCs with memory on package.
I'm surprised Apple haven't actually done a two-tier memory controller with on-package memory like the A/Mx chips use and a seperate 1/2x64-bit memory channel for higher RAM quantities. They could then do volume cheaper 8GB Mx chips and have more RAM externally - with decent memory management the performance hit would be managable as most application memory space is small and (except for a few specific types of workload/datasets) most extra RAM used for data and application caches doesn't necessarily need to be ultra-quick.
Sure you could have higher RAM densities packaged with the CPU but that is more expensive and then the RAM package heat also comes in to play a bit more.
AMD's caching on their GPUs essentially already does a similar function, but scale the cache size up and then it becomes much more useful. Wouldn't surprise me if Intel/AMD aren't working on something like this with forking off a memory controller from their CPU tile / adding an extra memory channel and RAM pads to the IO-die...
Problem is really relying on Linux kernel / Microsoft devs to implement memory management to leverage such a thing.
The margins on high end PC is so thin these days that even a 0.009v or 0.1Ghz can create instability, I'm not even going into the messy "Windows" parts. Of course I don't support Apple's BS pricing/options so "normal" PC will still be my choice for the foreseeable future!
CPU Boost is OC, that's why manual OC has only remnants.
I'm glad more reviewers and publications are starting to a) look at performance per watt, and b) look at performance with different power limits - it's starting to give people a clearer view of just how good/bad some products are at a core performance level and how much the higher end parts are being pushed to compete and take the 'performance crown'. Its been shown from several reviews now that with the thermal limits in place some of the K/KS SKUs are literally only good for a minor bump in speed - it's only a good look and a win if you ignore the crazy element.
When the 13900K with its 253W TDP was announced I was surprised it was being seen as more of a "yeah, it's a bit high" vs the "lol, you out 'bulldozered' AMD"...
Intel will no doubt push arrow lake for all it's worth and blow past that 125W TDP shown in the screenshot leak. It has a slightly larger die than raptor lake but a lot more logic on board so to a certain extent they may be able to control heat better. Will be interesting to see how good the idle efficiency is with all that extra logic sitting there...
Shame is that if the architecture performs great and scales well up until say 125W, they just will not take that win in that space. Although the media and everyone who buys stuff is to blame... "I want the best and damn the expense" has made a lot of flawed products a success.... I just think more the "damn the expense" part...
Even Apple have turned up the wick on their M parts a bit over time...
so I wish serious publications didn’t bother with it and left it to places like wccf and mlid so he rest of us aren’t bothered with it
We'll do that on the fly. :laugh:
I was initially confused by "Intel 4" and thought what the heck...
So far, we have had information that N3 is used for all K SKUs and 20A for non-K i5 and below.
This is the first time ever I am seeing Intel 4 associated with Arrow Lake. Weird...Also, we have never heard of Intel 4 being used on Arrow Lake. This is so weird...
Perhaps they had ES on several nodes and this might be an old screen-shot
For Arrow Lake, current leak suggest N3 and 20A.20A on lower SKUs and N3 on K and higher SKUs. Intel 4 screenshot perhaps shows one of old ES that they design on several nodes.Indeed. It has been released already on Sierra Forest CPUs. It's tailored for density and efficiency.
www.intel.com/content/www/us/en/products/sku/240362/intel-xeon-6780e-processor-108m-cache-2-20-ghz/specifications.html