Tuesday, October 1st 2024
AMD Announces New AGESA 1.2.0.2, 105W cTDP for 9700X and 9600X, Intercore Latency Improvements
AMD today made four key announcements for its Ryzen 9000 series "Granite Ridge" desktop processors based on the "Zen 5" microarchitecture. These mainly aim to improve upon the products as originally launched in August. To begin with, AMD announced a 105 W cTDP (configurable TDP) mode for the Ryzen 7 9700X and Ryzen 7 9600X processors, with full warranty coverage. This setting can be enabled in the UEFI setup program of a motherboard running its latest version of UEFI firmware, which encapsulates the AGESA ComboAM5 PI 1.2.0.2 microcode. The setting raises the PPT (package power tracking) value of the 9700X and 9600X to 140 W, and treats them as if they were 105 W TDP processors. These chips were originally launched by AMD with 65 W (88 W PPT), and as reviewers quickly found out, unlocking power improves performance at stock clock speeds, as it improves boost frequency residence of these chips.
Next up, is the AGESA PI 1.2.0.2 microcode itself, which introduces the 105 W cTDP mode for the 9700X and 9600X along with warranty coverage, which we just talked about; plus works to improve the core-to-core latency on the Ryzen 9 9900X and Ryzen 9 9950X. These are processors with two CPU complex dies (CCDs), each with either 8 or 6 cores enabled. To the software, this is still a single-socket (1P) CPU with 12 or 16 cores. Although some awareness of the dual-CCD architecture is added to the OS scheduler to help it localize certain kinds of workloads (such as games) to a single CCD, reviewers noted that core-to-core latency on the dual-CCD chips was still too high, which should affect performance when a software's threads are migrating between cores, or if a workload is multithreaded, such as media encoding. AMD addressed exactly this with the new AGESA PI 1.2.0.2 update.AMD describes the technical aspect of what was causing undesirably high core-to-core latency and erroneous core-parking during multithreaded workloads:
In the following weeks, you can expect memory manufacturers to launch new high-speed DDR5 memory kits with AMD EXPO profiles—speeds such as DDR5-6800, DDR5-7200, DDR5-7600, and DDR5-8000. AMD EXPO is similar to Intel XMP, it is an SPD extension that makes it easy for end-users to enable a memory kit's advertised speeds and timings in the UEFI setup program. EXPO covers all the sub-timings and voltages that are unique to Ryzen processors' memory architecture.Lastly, motherboards based on the AMD X870E and X870 chipsets should be available to purchase from today. AMD Ryzen 9000 series processors are compatible with AMD 600-series chipset motherboards using a firmware update (which can be done using UEFI BIOS Flashback); but the new crop of motherboards based on AMD 800-series chipset support these processors out of the box, besides introducing a few modern I/O features such as 40 Gbps USB4 and Wi-Fi 7 networking.
Next up, is the AGESA PI 1.2.0.2 microcode itself, which introduces the 105 W cTDP mode for the 9700X and 9600X along with warranty coverage, which we just talked about; plus works to improve the core-to-core latency on the Ryzen 9 9900X and Ryzen 9 9950X. These are processors with two CPU complex dies (CCDs), each with either 8 or 6 cores enabled. To the software, this is still a single-socket (1P) CPU with 12 or 16 cores. Although some awareness of the dual-CCD architecture is added to the OS scheduler to help it localize certain kinds of workloads (such as games) to a single CCD, reviewers noted that core-to-core latency on the dual-CCD chips was still too high, which should affect performance when a software's threads are migrating between cores, or if a workload is multithreaded, such as media encoding. AMD addressed exactly this with the new AGESA PI 1.2.0.2 update.AMD describes the technical aspect of what was causing undesirably high core-to-core latency and erroneous core-parking during multithreaded workloads:
This was mainly due to some corner cases where it takes two transactions to both read, and write, when information is shared across cores on different parts of a Ryzen 9 9000 series processor. However, we've been working on optimizing this since the launch of the 9000 series. In the new 1.2.0.2 BIOS update, we've managed to cut the number of transactions in half for this use case, which helps reduce core-to-core latency in multi-CCD models.AMD says that reviewers should still expect high values in core-to-core latency benchmarks, but in practice, performance in multithreaded workloads should improve, which can be verified by benchmarking across a typical set of processor benchmarks. The company says:
we've been working on optimizing this since the launch of the 9000 series. In the new 1.2.0.2 BIOS update, we've managed to cut the number of transactions in half for this use case, which helps reduce core-to-core latency in multi-CCD models. While this will show up on some core-to-core latency benchmarks, the real-world improvement is most noticeable in a very specific gaming scenario: in heavily threaded games that don't trigger core parking. Our lab tests suggest Metro, Starfield, and Borderlands 3 can show some uplift, as well as synthetic tests like 3DMark Time Spy.Next up, the company added official AMD EXPO support for DDR5-8000. With this generation, AMD introduced support for high DDR5 memory speeds using a 1:2 UCLK:MCLK ratio. We recently did a comprehensive study of how the Ryzen 9 9950X handles DDR5-8000, and whether you should use it over the DDR5-6000 sweetspot frequency. You can read all about it in our Zen 5 Memory Scaling article.
In the following weeks, you can expect memory manufacturers to launch new high-speed DDR5 memory kits with AMD EXPO profiles—speeds such as DDR5-6800, DDR5-7200, DDR5-7600, and DDR5-8000. AMD EXPO is similar to Intel XMP, it is an SPD extension that makes it easy for end-users to enable a memory kit's advertised speeds and timings in the UEFI setup program. EXPO covers all the sub-timings and voltages that are unique to Ryzen processors' memory architecture.Lastly, motherboards based on the AMD X870E and X870 chipsets should be available to purchase from today. AMD Ryzen 9000 series processors are compatible with AMD 600-series chipset motherboards using a firmware update (which can be done using UEFI BIOS Flashback); but the new crop of motherboards based on AMD 800-series chipset support these processors out of the box, besides introducing a few modern I/O features such as 40 Gbps USB4 and Wi-Fi 7 networking.
33 Comments on AMD Announces New AGESA 1.2.0.2, 105W cTDP for 9700X and 9600X, Intercore Latency Improvements
Today's chips tend to boost as much as possible until some limit is met. This works for my Zen 3: when I raise PPT limit without touching anything else, the only difference is that few other cores boost a few hundred MHz more until the CPU package hits the newly set TDP limit or the EDP limit (whatever comes first). I've never tried this myself but maybe if you set 200W TDP limit for 65W CPU, it will try to boost all cores to reach max. boost clock limit and still it may never really reach 200W limit.
With PBO you also change voltage curve and max. boost clock. PBO is not guaranteed and can render your CPU unstable. This could mean another potential fiasco for AMD so I think they will skip using PBO for this update.
65W is efficient, 105W is crazily inefficient but 15% faster is faster if that specific workload matters to you - and as always a manual tune with PBO+ and some curve optimiser will likely get those who are willing to tinker the absolute best of both worlds.
65W cTDP = 88W PPT
Whichever way you slice, they are not "roughly same" power consumption/thermals.