Tuesday, July 27th 2021

Intel Rebadges 10nm Enhanced SuperFin Node as "Intel 7," Invents Other Creative Node Names

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Jul 26th, 2021 15:57 Updated: Jul 27th, 2021 02:27 Discuss (101 Comments)

Intel, in a move comparable to its competitors' Performance Rating system from the 1990s, has invented a new naming scheme for its in-house foundry nodes to claim technological parity with contemporaries such as TSMC and Samsung, that are well into the sub-10 nm class. Back in the i586 era, when Intel's competitors such as AMD and Cyrix, couldn't keep up with its clock-speeds yet found their chips to be somewhat competitive, they invented the PR (processor rating) system, with a logical number attempting to denote parity with an Intel processor's clock-speed. For example, a PR400 processor rating meant that the chip rivaled a Pentium II 400 MHz (which it mostly didn't). The last that the PR system made sense was with the final generation of single-core performance chips, Pentium 4 and Athlon XP, beyond which, the introduction of multi-core obfuscated the PR system. A Phenom X4 9600 processor didn't mean performance on par with a rival Intel chip running at an impossible 9.60 GHz.

Intel's new foundry naming system sees its 10 nm Enhanced SuperFin node re-badge as "Intel 7." The company currently builds 11th Gen Core "Tiger Lake" processors on the 10 nm SuperFin node, and is expected to build its upcoming 12th Gen Core "Alder Lake" chips on its refinement, the 10 nm Enhanced SuperFin, which will now be referred to as "Intel 7." The company is careful to avoid using the nanometer unit next to the number, instead signaling the consumer that the node somehow offers transistor density and power characteristics comparable to a 7 nm node. Intel 7 offers a 10-15 percent performance/Watt gain over 10 nm SuperFin, and is already in volume production, with a debut within 2021 with "Alder Lake."

This is where things get interesting. The successor to Intel 7 is named Intel 4, and is technically a 7 nm EUV node. This node offers a 20 percent performance/Watt gain over Intel 7 (aka 10 nm Enhanced SuperFin), and will debut in mid-2022 with "Meteor Lake" client- and "Granite Rapids" enterprise processors. Intel has gone with "4" for the name as 2022 sees both Samsung and TSMC roll out their sub-5 nm nodes. TSMC will debut the 4 nm, while Samsung will hopefully iron out its 5 nm yield issues, and ramp up 4 nm, by 2022.

Intel 3 succeeds Intel 4 in the second half of 2023, and is timed to launch around the time TSMC comes out with its sub-4 nm node, likely the 2 nm. Intel claims this node offers an 18 percent performance/Watt gain over the Intel 4, implement a denser HP library, increase the use of EUV, improve the drive-current and via resistance, to result in the performance/Watt target. With no mention of FET size, it's very likely that Intel 3 is still a 7 nm node.

It's only in 2024 that Intel is promising major technological breakthroughs, with Intel 20A, heralding the era in silicon fabrication where transistor sizes are measured in Angstroms (0.1 nm). 20A would hence be a creative way of saying 2 nm. Intel will introduce a brand new transistor design it calls the RibbonFET. It remains to be seen if this is a whole new innovation or similar to nanosheet FETs. Intel is also announcing PowerVia, a revolutionary new way to connect silicon dies with each other, or with the package, which debuts with the Intel 20A node. The company is targeting a 1H-2024 debut of this new node.

With these, Intel is ensuring that it has a new node to offer each year leading up to 2024, each with a double-digit percent performance/Watt gain, so the company can restore something resembling its "Tick-Tock" product development cadence, enabling it to compete not just against AMD, but also the emergence of serious Arm-powered rivals, such as NVIDIA, Qualcomm, and Apple. The company is hence facing similar levels of competition as the early 1990s. x86 may no longer have a stranglehold over the PC, as Arm-powered rivals claw away at market-share with efficient and fairly-powerful chips.

The complete slide-deck follows.

Source: VideoCardz

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101 Comments on Intel Rebadges 10nm Enhanced SuperFin Node as "Intel 7," Invents Other Creative Node Names

#76

R0H1T

Why_MeIf they weren't a noob they wouldn't be asking a minimum wage Best Buy employee for PC hardware advice.

Well it's not like Intel or even AMD at times make it easy for them, do they? There's two vastly different Intel "10th gen" chips out there, do you remember them by the model numbers, process node or uarch heck (differentiating) feature set et al?

#77

InVasMani

Gruffalo.SoldierBoth 10nm Enhanced SuperFin
Alder Lake's smaller Gracemont cores jump forward a single Atom generation and offer the benefit of being more power and area efficient (perf/mm^2) than the larger Golden Cove cores. Gracemont also comes with increased vector performance, a nod to an obvious addition of some level of AVX support (likely AVX2). Intel also lists improved single-threaded performance for the Gracemont cores.

The 6 + 8 design is the one I've got my eye one. I'm a little surprised Intel did do 2 + 8 or a 4+ 8 design though. They could be quite compelling on price while offering a good bit of additional background and parallel task processing.

#78

Why_Me

R0H1TWell it's not like Intel or even AMD at times make it easy for them, do they? There's two vastly different Intel "10th gen" chips out there, do you remember them by the model numbers, process node or uarch heck (differentiating) feature set et al?

Do you think your average buyer is going to ask that from a Best Buy employee? Anyone with tech knowledge is going to get their tech info from sites such as this one. Working at Best Buy is one step up from asking customers if they want fries with their burger.

#79

medi01

Tom YumHow about real world applications

How about thinking about it a bit more?
Transistor density of the node is not everything, architecture has a great impact. (e.g. AMD used to cram lots more transistors in Polaris than NV did with Pascal)

That is why L1 cache vs L1 cache was compared.

And, it was 22 by 22 for "7nm TSMC" and 24 by 24 for "14nm Intel". (yes, FOURTEEN, not ten)

Intel's 10nm might be closer to actual 7nm, than TSMC's.

#80

Chrispy_

When you can't meet performance expectations, just tell lies!
10 = 7 when truth isn't a requirement :)

#81

Ravenas

medi01How about thinking about it a bit more?
Transistor density of the node is not everything, architecture has a great impact. (e.g. AMD used to cram lots more transistors in Polaris than NV did with Pascal)

That is why L1 cache vs L1 cache was compared.

And, it was 22 by 22 for "7nm TSMC" and 24 by 24 for "14nm Intel". (yes, FOURTEEN, not ten)

Intel's 10nm might be closer to actual 7nm, than TSMC's.

The power consumption says differently.

#82

Punkenjoy

RavenasThe power consumption says differently.

True, but the power consumption is not only dependent on the node. I can also be dependent on the architecture and on the v-curve intel implement.

That is back to the point i made. Only the real world performance (and power consumption) matter, not the number on the fabrication node.

#83

Ravenas

PunkenjoyTrue, but the power consumption is not only dependent on the node. I can also be dependent on the architecture and on the v-curve intel implement.

That is back to the point i made. Only the real world performance (and power consumption) matter, not the number on the fabrication node.

The loser always wants to rewrite the narrative. I would love to see Intel return to the best fab in the world, it just isn’t so.

I thought Intel hired an Engineer to take the helm, not a marketing guy.

#84

mtcn77

RavenasI thought Intel hired an Engineer to take the helm, not a marketing guy.

Engineering roadmap problems have been out in the open for almost a decade.

Don't try to drive your message home too hard. Power is indeed the best benchmark to size good foundries.

We can let the performance speak for itself in marketing. It will right itself anyway in regard to the goals it delivered upon.

#85

Ravenas

mtcn77Engineering roadmap problems have been out in the open for almost a decade.

Don't try to drive your message home too hard. Power is indeed the best benchmark to size good foundries.

We can let the performance speak for itself in marketing. It will right itself anyway in regard to the goals it delivered upon.

I don’t need to drive a message home, Intel is already doing that for me. Hide the valley numbers in effort to distract from the fact that Intel simply can’t keep up with TSMC.

#86

mtcn77

RavenasI don’t need to drive a message home, Intel is already doing that for me. Hide the valley numbers in effort to distract from the fact that Intel simply can’t keep up with TSMC.

You said power doesn't matter. Power and performance don't mix. If one is good, the other may or may not be so favourable. Don't create a false dichotomy. Intel may or may not deliver a good 10nm node that might have fewer cores, but score similarly, "if power is toned down measurably."

#87

Ravenas

mtcn77You said power doesn't matter. Power and performance don't mix. If one is good, the other may or may not be so favourable. Don't create a false dichotomy. Intel may or may not deliver a good 10nm node that might have fewer cores, but score similarly, "if power is toned down measurably."

Putting out a product with good single core performance at the cost of low overall performance and enormous power consumption doesn’t sound great. Probably why the their products are literally available i5 through i7.

Now let’s start being less transparent with our customers.

Great ideas coming out of Intel.

#88

mtcn77

RavenasPutting out a product with good single core performance at the cost of enormous overall performance and low power consumption doesn’t sound great.

Well, it is Intel's problem. You still make the argument power goes hand in hand with performance which is not how nodes are tuned. They are low power and high power, so there is no single factor, like the number code, that is deterministic...

#89

Ravenas

mtcn77Well, it is Intel's problem. You still make the argument power goes hand in hand with performance which is not how nodes are tuned. They are low power and high power, so no single factor as the node number...

The node plays in to power consumption obviously. Physics is a stubborn subject. Not sure where you are going beyond hang on to some forum ego.

#90

mtcn77

RavenasThe node plays in to power consumption obviously. Physics is a stubborn subject. Not sure where you are going beyond hang on to some forum ego.

You constantly make the argument Intel cannot make an efficient 10nm node which is quite not the same as Intel not making a 7nm node. I am not going anywhere without taking you along the journey with me. We might have differences of opinion, but physics rules are constants. Power depends on the backend as much as the frontend. If Intel make copper lines go big, resistance takes a dip, power goes down, dynamic power can scale up more. Like vertical ram, I cannot vouch with a resounding yes that the design will not beat the miniaturization in the end. I get it Intel started the rat race, but that isn't our problem.

#91

Ravenas

mtcn77You constantly make the argument Intel cannot make an efficient 10nm node which is quite not the same as Intel not making a 7nm node. I am not going anywhere without taking you along the journey with me. We might have differences of opinion, but physics rules are constants. Power depends on the backend as much as the frontend. If Intel make copper lines go big, resistance takes a dip, power goes down, dynamic power can scale up more. Like vertical ram, I cannot vouch with a resounding yes that the design will not beat the miniaturization in the end. I get it Intel started the rat race, but that isn't our problem.

7 nm and 10 nm nodes don’t exist at Intel. What are you talking about?

The wool hasn’t been pulled over your eyes yet?

#92

mtcn77

Ravenas10 nm nodes don’t exist at Intel.

Not true. This is a nice explanation why our discussion has been quite fruitless. No need to fight tooth and nail about it.

#93

Ravenas

mtcn77Not true. This is a nice explanation why our discussion has been quite fruitless. No need to fight tooth and nail about it.

Absolutely true. Intel will no longer provide node dimensions. Why speak in it anymore?

I didn’t realize we are fighting tooth and nail about anything…

My stance is I want customer transparency and node plays in to power consumption. Your stance is, no no no there is more!!! Obviously. I never argued there wasn’t. Where was I fighting tooth and nail?

#94

mtcn77

RavenasIntel will no longer provide node dimensions.

Well, not that it matters now since it has been a matter of fact. They cannot delete its existence from the past and we will forever know of a 10nm node now and then later.
What is going to be different is the information gap between foundry node scaling factor and marketing factor will close because let us accept that it was always a marketing tool in the first place. Now, Intel won't market what it cannot deliver, so we will stop focusing whether the new node is 2.7 times, or 2.4 times more advanced in regard to the former one. This was a substitution for the real factor which was the cell size, not the Moore's Law like you accept it. It never was constant, it was just how Intel demonstrated it to be since they never, actually, wanted to be good, only "good enough", when in comparison to IBM when this numeric codes first sprung up.

RavenasMy stance is I want customer transparency

This is what Intel wants you to believe it to be since IBM times is all I'm saying. There is nothing transparent about it is all I'm saying. It is just a marketing 'hook'..

#95

IceShroom

londisteI would actually like to see your source about this.
Industry and technical analysts all are in a pretty nice agreement that Intel's 10nm is in the same group with TSMC/Samsung 7nm. Similarly Intel's 7nm in the same group with TSMC/Samsung 5nm.

Mobile chips are from a different variation of manufacturing process. 90% of theoretical density is rather normal for that.
High performance chips come with a much lower density, from all manufacturers.

You are right about Intel not having real implementation with max density in a product . On the other hand, I have no idea what in their product portfolio would not be using the high performance variation. IIRC Intel has said their 10nm has two high performance variations with 80 MTr/mm2 and 65 MTr/mm2.

At the same time, I cannot think of anything from Samsung's 7nm that would be on high performance variation. The main use so far are the mobile SoCs. Can you think of something Samsung has manufactured?

Edit:
Apparently Intel did have a kind of product with high density in the 10nm failure times. i3-8121U had 100.8 MTr/mm2: Intel 10 nm Logic Process Analysis (Cannon Lake) | TechInsights

Those "Tech analyst" just repeating Intel's marketing lines. If Intel's 10nm is so dense they why Intel not publishing official number?? Company do that when they dont have real winner in hand. If Intel realy had better 10nm then they would have published its real
Samsung's 7nm may not have high power chip, but their 8nm has 350W+ chip with 46MT/mm2 [Nvidia A102 Chip]. What is the density of Intel's 28W-45W Tiger Lake chips??? And TSMC's 7nm has chip with 400W+ with 60MT/mm2+ [Nvidia A100 Chip, AMD Renoir, Cezenne] and and 80MT/mm2+ mobile SoC's[Huawei Kirin 990 5G,980 kwown]. What is on Intel's 10nm Lake field?? It was low power mobile chip and according to this photo [not official, take a grain of salt] it has only 49.39 MT/mm2 same or lower then TSMC's 10nm. Nowhere near as TSMC's 7nm.

According to same kind of analyst cold fusion is also possible[But only on paper, no real implementation and not possible according to physics].

Edit:
Apparently Intel did have a kind of product with high density in the 10nm failure times. i3-8121U had 100.8 MTr/mm2: Intel 10 nm Logic Process Analysis (Cannon Lake) | TechInsights

Just repeating Intel's marketing slide. No real analysis.

#96

chrcoluk

If the efficiency is there to match 7nm then fair enough, we will see.

#97

londiste

IceShroomIf Intel's 10nm is so dense they why Intel not publishing official number?

Where do you think 100.76 number comes from?

#98

rbgc

Disappointment. I expected it will be Intel 6, Intel 3 and Intel 2.

#99

IceShroom

londisteWhere do you think 100.76 number comes from?

Same place as the Cold fusion. Exists on theory, not really implementable.

#100

Vayra86

TheLostSwedeDear Intel, the unit is Å, not A, as his name was Ångström. I guess your marketing department couldn't figure out how to type it, so now your new nodes are in Ampere...

They're just predicting the amount of amps required for idling on those cpus by then. Remember, everything's a roadmap these days.

Intel 7. So its an i7 on Intel 7. You can really tell and see Pat's engineering influence is working out just fine. So glad they have real brains up there now. Even my 8700K feels a bit faster being on Intel 14 now. Fat Fins instead of Super, but still. Thanks, Pat!

medi01How about thinking about it a bit more?
Transistor density of the node is not everything, architecture has a great impact. (e.g. AMD used to cram lots more transistors in Polaris than NV did with Pascal)

That is why L1 cache vs L1 cache was compared.

And, it was 22 by 22 for "7nm TSMC" and 24 by 24 for "14nm Intel". (yes, FOURTEEN, not ten)

Intel's 10nm might be closer to actual 7nm, than TSMC's.

And yet it doesn't perform as such, strange how that works then. It underlines that architecture indeed has impact. The choice of what you place on a die, for example, also determines the density. Regardless, TSMC is producing 7nm on an EUV process and ever since DUV was left behind, the node performs as it should compared to its predecessors.

So forget density, start thinking lithography and how to get there. Its the chip quality that determines the frequency options for example, and the binning.

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Intel Rebadges 10nm Enhanced SuperFin Node as "Intel 7," Invents Other Creative Node Names

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