Friday, February 14th 2025
AMD Zen 6 Powers "Medusa Point" Mobile and "Olympic Ridge" Desktop Processors
AMD is readying two important client segment processors powered by the next-generation "Zen 6" microarchitecture, according to a sensational new report by Moore's Law is Dead. These are the "Medusa Point" mobile processor, and the "Olympic Ridge" desktop. The former is a BGA roughly the size and Z-Height of the current "Strix Point," but the latter is being designed for the existing Socket AM5, making it the third (and probably final) microarchitecture to do so. If you recall, Socket AM4 served three generations of Zen, not counting the refreshed "Zen+." At the heart of the effort is a new CPU complex die (CCD) that AMD plans to use across its client and server lineup.
The "Zen 6" performance CCD is being designed for a 3 nm-class node, likely the TSMC N3E. This node promises a significant increase in transistor density, power, and clock speed improvements over the current TSMC N4P node being used to build the "Zen 5" CCD. Here's where it gets interesting. The CCD contains twelve full-sized "Zen 6" cores, marking the first increase in core-counts of AMD's performance cores since its very first "Zen" CCD. All 12 of these cores are part of a single CPU core complex (CCX), and share a common L3 cache. There could be a proportionate increase in cache size to 48 MB. AMD is also expected to improve the way the CCDs communicate with the I/O die and among each other.
Going all the way back to the Ryzen 3000 series "Matisse," the two CCDs on the client desktop processor have had Infinity Fabric links to the I/O die, but no direct high-bandwidth interconnects between the two CCDs. For threads to migrate between cores of the two CCDs, they would have to make a round-trip through the main memory. AMD is looking to solve this with the introduction of a new low-latency bridge connection between the two CCDs. If the goal is to enable threads to seamlessly migrate among cores of the two CCDs, cutting out round-trips to the main memory, then the purpose of this bridge interconnect is to establish cache coherency between the two CCDs. This would vastly lower intercore latency.
Here's where things get very interesting. Apparently, the "Medusa Point" mobile processor is chiplet-based, and will use a single 12-core "Zen 6" chiplet, with a large mobile client I/O die built on an older node, likely the N4P. This mobile cIOD will contain an updated iGPU that's powered by the newer RDNA 4 graphics architecture. It will also contain the chip's memory controllers, and an updated NPU. We hope AMD works to increase the number of PCIe lanes put out by this I/O die, or at least update it to PCIe Gen 5. Pictures show small rectangular structures on the mobile client I/O die causing some speculation that it is some kind of low power island CCX with "Zen 6c" cores, although MLID lays this to rest by saying that these are workgroup processors (WGPs) of the iGPU. There are eight of these and a large slab of L2 cache, which seems to confirm that the iGPU is based on the RDNA 4 graphics architecture, and has 16 compute units (CU).
Since AMD is using the same CCD for "Medusa Point" as the "Olympic Ridge" desktop processor, you could expect variants of "Medusa Point" with 3D V-Cache. The 3D V-Cache technology is expected to be implemented on "Zen 6" much in the same way it is on "Zen 5," with an upside-down stacking—3D V-Cache die (L3D) below, with CCD on top.
Given the increase in CPU core counts, especially with "Olympic Ridge" getting up to 24 cores with two CCDs, and the inter-CCD bridge interconnect for cache coherency, AMD is going to need a new client I/O die for desktop. We've already discussed this in older articles. The new cIOD is expected to be built on the Samsung 4LPP (4 nm EUV) foundry node, which offers improvements over the TSMC N6 DUV node the current cIOD is being built on. A key area of focus for AMD will be the memory controllers, which will be updated to support higher DDR5 memory speeds using technologies such as CKD. You can currently run a "Granite Ridge" processor with memory speeds of up to DDR5-8000 but using a 1:2 clock divider is engaged between FCLK and MCLK, with 1:1 speeds being limited to around DDR5-6400. The new memory controllers will look to increase speeds with 1:1, and unlock speeds beyond 10000 MT/s with 1:2.
Then there's the matter of AI acceleration, and the new cIOD will present AMD with the opportunity to implement at least a 50 TOPS-class XDNA 2 NPU. Intel received flack for giving its "Arrow Lake" processors a 16 TOPS-class NPU that doesn't meet Copilot+ requirements, and the company is probably working to fix this in "Panther Lake," and so if AMD decides to implement an NPU on the cIOD for "Olympic Ridge," we predict it will be at least 50 TOPS-class.
Source:
Moore's Law is Dead
The "Zen 6" performance CCD is being designed for a 3 nm-class node, likely the TSMC N3E. This node promises a significant increase in transistor density, power, and clock speed improvements over the current TSMC N4P node being used to build the "Zen 5" CCD. Here's where it gets interesting. The CCD contains twelve full-sized "Zen 6" cores, marking the first increase in core-counts of AMD's performance cores since its very first "Zen" CCD. All 12 of these cores are part of a single CPU core complex (CCX), and share a common L3 cache. There could be a proportionate increase in cache size to 48 MB. AMD is also expected to improve the way the CCDs communicate with the I/O die and among each other.
Here's where things get very interesting. Apparently, the "Medusa Point" mobile processor is chiplet-based, and will use a single 12-core "Zen 6" chiplet, with a large mobile client I/O die built on an older node, likely the N4P. This mobile cIOD will contain an updated iGPU that's powered by the newer RDNA 4 graphics architecture. It will also contain the chip's memory controllers, and an updated NPU. We hope AMD works to increase the number of PCIe lanes put out by this I/O die, or at least update it to PCIe Gen 5. Pictures show small rectangular structures on the mobile client I/O die causing some speculation that it is some kind of low power island CCX with "Zen 6c" cores, although MLID lays this to rest by saying that these are workgroup processors (WGPs) of the iGPU. There are eight of these and a large slab of L2 cache, which seems to confirm that the iGPU is based on the RDNA 4 graphics architecture, and has 16 compute units (CU).
Since AMD is using the same CCD for "Medusa Point" as the "Olympic Ridge" desktop processor, you could expect variants of "Medusa Point" with 3D V-Cache. The 3D V-Cache technology is expected to be implemented on "Zen 6" much in the same way it is on "Zen 5," with an upside-down stacking—3D V-Cache die (L3D) below, with CCD on top.
Given the increase in CPU core counts, especially with "Olympic Ridge" getting up to 24 cores with two CCDs, and the inter-CCD bridge interconnect for cache coherency, AMD is going to need a new client I/O die for desktop. We've already discussed this in older articles. The new cIOD is expected to be built on the Samsung 4LPP (4 nm EUV) foundry node, which offers improvements over the TSMC N6 DUV node the current cIOD is being built on. A key area of focus for AMD will be the memory controllers, which will be updated to support higher DDR5 memory speeds using technologies such as CKD. You can currently run a "Granite Ridge" processor with memory speeds of up to DDR5-8000 but using a 1:2 clock divider is engaged between FCLK and MCLK, with 1:1 speeds being limited to around DDR5-6400. The new memory controllers will look to increase speeds with 1:1, and unlock speeds beyond 10000 MT/s with 1:2.
Then there's the matter of AI acceleration, and the new cIOD will present AMD with the opportunity to implement at least a 50 TOPS-class XDNA 2 NPU. Intel received flack for giving its "Arrow Lake" processors a 16 TOPS-class NPU that doesn't meet Copilot+ requirements, and the company is probably working to fix this in "Panther Lake," and so if AMD decides to implement an NPU on the cIOD for "Olympic Ridge," we predict it will be at least 50 TOPS-class.
91 Comments on AMD Zen 6 Powers "Medusa Point" Mobile and "Olympic Ridge" Desktop Processors
And you're right, it's not just about core counts, it's about progress. AMD was offering cheap CPUs with early Ryzens, and the first few generations offered huge improvements in all aspects. Then they found themselves ahead of Intel with Zen 3, and they suddenly became greedy, which is what you do when you're ahead. The 9600X was still a 6-core CPU, the generational improvement was abysmal, but they still charged almost $300 for it.
As a consumer you should be advocating for progress. We had 4-core Intel CPUs in the mainstream for almost a decade when AMD had nothing. It's time to make 8 cores the baseline.
But in all fairness if the selected node is much better than the ArrowLake maybe they can do it. Maybe not 52 in total but 32-40.
AMD is rumored to preparing APUs up to ~40 mixed Zen6/6c cores. 8~12 Zen6 + more Zen6c, but I think those 6c will play different role than Intel’s E-cores.
1. 12-core 9900X is on par on average in applications with 20-core 265K
2. 8-core 9800X3D is 4-5% faster on average in applications than 14-core 245K and only 12% slower than 20-core 265K
3. 6-core 9600X is only 13% slower on average in applications than 14-core 245K
12-13% is a "drastic" difference on small core count CPUs, indeed...
www.techpowerup.com/review/amd-ryzen-7-9800x3d/27.htmlYou started with dubious core count narrative, now you introduce other variables, such as uplift and price. You need to decide what your narrative is actually about, because you are now suddenly spinning several balls in the air, not just core count.I always advocate for progress, but 8 cores does not need to be "the" baseline because consumers have complained for a long time that entry CPUs are not that common. There need to be entry CPUs too, such as R5 9600 or R5 8500G, and those do not need 8 big cores. With Zen6, 8 cores might become the new entry point CPU, but we will need to see how this pans out. I still prefer to see 6-core SKUs too, so that devices like NAS are not artificially more expensive, where more than 6 cores is not needed to run such a product.
However, as published recently by Passmark, both AMD and Intel CPUs have flattened in performance uplift with the last generation of desktop CPUs, excluding X3D, somewhat. So, yes, it looks like we have reached the plateau with current architectures and features on retail CPUs, but this is not an analogy for "4-core era". Zen6 and Nova Lake should bring progress in several segments and features beyond higher core count. Both companies push forward, as they should.
8 cores have been the baseline for AMD's design since 2017. It's definitely time to move up after 8 years, those chiplets have gotten really tiny. Core counts need to be raised across all tiers, no question about it.
They will still have a plethora of other core configuration options for different segments: 4+4 Kracken and 4+8 Strix refresh for lower power devices, as well as 8-core chiplets for embedded and edge segments. Plenty of options for diverse usage cases.
Finally 16+ cores on a "regular" desktop CPU at AMD :toast:
If 12core CCDs are actually true then that will be the main full chiplet at least for desktop.
Just wanted to say that because the way you phrase it looked like they are preparing chiplets of 12, 16, 32.
Desktop CCDs will be 12core, and CPUs up to 24cores with 2x full 12core CCDs.
If let’s say they will go down to 8cores (4 disabled, 33%), it will give AMD the opportunity to cook CPUs with combinations of 8,10,12 cores with a total of 8, 10, 12, 16, 18, 20, 22, 24 cores. All full Zen6 cores. 6/6c mix for the APUs and that will be a different story.
Not saying that they will use all these for desktop, but they can if they want depending on fab yields.
I’m down!
I'd introduce Ryzen R4, R6, R8 and R10. No reason to have SKUs with odd numbers only, to mirroiw what Intel does.
Also, it looks like there would not be mixed Zen6/6c for APUs. They seem to have abandoned mixed design for Zen6. Again, we will more once more leaks emerge and corroborate this info.GMI, or Infinity Fabric, will be replaced by Infinity Link, which is evolved version of what we can see on Navi 31 as the interconnect between MCD and GCD. Infinity Link will bring multiple times more bandwidth, lower latency and much better power efficiency. Zen6 shapes to be "Zen2" moment in improvements.
(And no, making them blurry and having washed out colors doesn't make the more credible…)Why? :rolleyes:
Because core count needs to increase every few years because someone said so?
Don't you know that there are diminishing returns with increasing core count (except for async batch workloads, mostly server loads), with a fairly sharp drop-off around ~8 cores. And in the event that you want to really put sustained load on lots of cores you need headroom in power and thermals too, like on a Threadripper.
Let's say someone managed to release a 4-core with 2x the core speed over current gen CPUs, would you buy that over an 8-core?
Most will say no, but that only tells us how little most people know about software scaling.
While that kind of difference may not be realistic in one generational jump, it illustrates a point about how extremely opinionated most enthusiasts are without any real basis in facts.If these were genuine marketing slides, it would imply the final product was only a few months away. Somehow I doubt that…