Friday, February 14th 2025
AMD Zen 6 Powers "Medusa Point" Mobile and "Olympic Ridge" Desktop Processors
AMD is readying two important client segment processors powered by the next-generation "Zen 6" microarchitecture, according to a sensational new report by Moore's Law is Dead. These are the "Medusa Point" mobile processor, and the "Olympic Ridge" desktop. The former is a BGA roughly the size and Z-Height of the current "Strix Point," but the latter is being designed for the existing Socket AM5, making it the third (and probably final) microarchitecture to do so. If you recall, Socket AM4 served three generations of Zen, not counting the refreshed "Zen+." At the heart of the effort is a new CPU complex die (CCD) that AMD plans to use across its client and server lineup.
The "Zen 6" performance CCD is being designed for a 3 nm-class node, likely the TSMC N3E. This node promises a significant increase in transistor density, power, and clock speed improvements over the current TSMC N4P node being used to build the "Zen 5" CCD. Here's where it gets interesting. The CCD contains twelve full-sized "Zen 6" cores, marking the first increase in core-counts of AMD's performance cores since its very first "Zen" CCD. All 12 of these cores are part of a single CPU core complex (CCX), and share a common L3 cache. There could be a proportionate increase in cache size to 48 MB. AMD is also expected to improve the way the CCDs communicate with the I/O die and among each other.
Going all the way back to the Ryzen 3000 series "Matisse," the two CCDs on the client desktop processor have had Infinity Fabric links to the I/O die, but no direct high-bandwidth interconnects between the two CCDs. For threads to migrate between cores of the two CCDs, they would have to make a round-trip through the main memory. AMD is looking to solve this with the introduction of a new low-latency bridge connection between the two CCDs. If the goal is to enable threads to seamlessly migrate among cores of the two CCDs, cutting out round-trips to the main memory, then the purpose of this bridge interconnect is to establish cache coherency between the two CCDs. This would vastly lower intercore latency.
Here's where things get very interesting. Apparently, the "Medusa Point" mobile processor is chiplet-based, and will use a single 12-core "Zen 6" chiplet, with a large mobile client I/O die built on an older node, likely the N4P. This mobile cIOD will contain an updated iGPU that's powered by the newer RDNA 4 graphics architecture. It will also contain the chip's memory controllers, and an updated NPU. We hope AMD works to increase the number of PCIe lanes put out by this I/O die, or at least update it to PCIe Gen 5. Pictures show small rectangular structures on the mobile client I/O die causing some speculation that it is some kind of low power island CCX with "Zen 6c" cores, although MLID lays this to rest by saying that these are workgroup processors (WGPs) of the iGPU. There are eight of these and a large slab of L2 cache, which seems to confirm that the iGPU is based on the RDNA 4 graphics architecture, and has 16 compute units (CU).
Since AMD is using the same CCD for "Medusa Point" as the "Olympic Ridge" desktop processor, you could expect variants of "Medusa Point" with 3D V-Cache. The 3D V-Cache technology is expected to be implemented on "Zen 6" much in the same way it is on "Zen 5," with an upside-down stacking—3D V-Cache die (L3D) below, with CCD on top.
Given the increase in CPU core counts, especially with "Olympic Ridge" getting up to 24 cores with two CCDs, and the inter-CCD bridge interconnect for cache coherency, AMD is going to need a new client I/O die for desktop. We've already discussed this in older articles. The new cIOD is expected to be built on the Samsung 4LPP (4 nm EUV) foundry node, which offers improvements over the TSMC N6 DUV node the current cIOD is being built on. A key area of focus for AMD will be the memory controllers, which will be updated to support higher DDR5 memory speeds using technologies such as CKD. You can currently run a "Granite Ridge" processor with memory speeds of up to DDR5-8000 but using a 1:2 clock divider is engaged between FCLK and MCLK, with 1:1 speeds being limited to around DDR5-6400. The new memory controllers will look to increase speeds with 1:1, and unlock speeds beyond 10000 MT/s with 1:2.
Then there's the matter of AI acceleration, and the new cIOD will present AMD with the opportunity to implement at least a 50 TOPS-class XDNA 2 NPU. Intel received flack for giving its "Arrow Lake" processors a 16 TOPS-class NPU that doesn't meet Copilot+ requirements, and the company is probably working to fix this in "Panther Lake," and so if AMD decides to implement an NPU on the cIOD for "Olympic Ridge," we predict it will be at least 50 TOPS-class.
Source:
Moore's Law is Dead
The "Zen 6" performance CCD is being designed for a 3 nm-class node, likely the TSMC N3E. This node promises a significant increase in transistor density, power, and clock speed improvements over the current TSMC N4P node being used to build the "Zen 5" CCD. Here's where it gets interesting. The CCD contains twelve full-sized "Zen 6" cores, marking the first increase in core-counts of AMD's performance cores since its very first "Zen" CCD. All 12 of these cores are part of a single CPU core complex (CCX), and share a common L3 cache. There could be a proportionate increase in cache size to 48 MB. AMD is also expected to improve the way the CCDs communicate with the I/O die and among each other.
Here's where things get very interesting. Apparently, the "Medusa Point" mobile processor is chiplet-based, and will use a single 12-core "Zen 6" chiplet, with a large mobile client I/O die built on an older node, likely the N4P. This mobile cIOD will contain an updated iGPU that's powered by the newer RDNA 4 graphics architecture. It will also contain the chip's memory controllers, and an updated NPU. We hope AMD works to increase the number of PCIe lanes put out by this I/O die, or at least update it to PCIe Gen 5. Pictures show small rectangular structures on the mobile client I/O die causing some speculation that it is some kind of low power island CCX with "Zen 6c" cores, although MLID lays this to rest by saying that these are workgroup processors (WGPs) of the iGPU. There are eight of these and a large slab of L2 cache, which seems to confirm that the iGPU is based on the RDNA 4 graphics architecture, and has 16 compute units (CU).
Since AMD is using the same CCD for "Medusa Point" as the "Olympic Ridge" desktop processor, you could expect variants of "Medusa Point" with 3D V-Cache. The 3D V-Cache technology is expected to be implemented on "Zen 6" much in the same way it is on "Zen 5," with an upside-down stacking—3D V-Cache die (L3D) below, with CCD on top.
Given the increase in CPU core counts, especially with "Olympic Ridge" getting up to 24 cores with two CCDs, and the inter-CCD bridge interconnect for cache coherency, AMD is going to need a new client I/O die for desktop. We've already discussed this in older articles. The new cIOD is expected to be built on the Samsung 4LPP (4 nm EUV) foundry node, which offers improvements over the TSMC N6 DUV node the current cIOD is being built on. A key area of focus for AMD will be the memory controllers, which will be updated to support higher DDR5 memory speeds using technologies such as CKD. You can currently run a "Granite Ridge" processor with memory speeds of up to DDR5-8000 but using a 1:2 clock divider is engaged between FCLK and MCLK, with 1:1 speeds being limited to around DDR5-6400. The new memory controllers will look to increase speeds with 1:1, and unlock speeds beyond 10000 MT/s with 1:2.
Then there's the matter of AI acceleration, and the new cIOD will present AMD with the opportunity to implement at least a 50 TOPS-class XDNA 2 NPU. Intel received flack for giving its "Arrow Lake" processors a 16 TOPS-class NPU that doesn't meet Copilot+ requirements, and the company is probably working to fix this in "Panther Lake," and so if AMD decides to implement an NPU on the cIOD for "Olympic Ridge," we predict it will be at least 50 TOPS-class.
90 Comments on AMD Zen 6 Powers "Medusa Point" Mobile and "Olympic Ridge" Desktop Processors
- after Nvidia or Intel support
or
- in a few years
AMD will lose sales and it will damage the Ryzen brand if they decide to cheap out on the NPU because "people will use the GPU" or "people don't care yet about an NPU".
Their RX 7000 series, in my opinion, wasn't a success because they thought that "people don't care yet about RT performance".
Ryzen 4 11400X 6 cores
Ryzen 5 11500X 8 cores
Ryzen 6 11600X 10 cores
Ryzen 7 11700X 12 cores
Ryzen 8 11800X 16 cores
Ryzen 9 11900X 20 cores
Ryzen 10 11960X 24 cores
www.techpowerup.com/332396/amd-reiterates-belief-that-2025-is-the-year-of-the-ai-pc
The idea of AI noise cancellation intrigues me if it offers real time active cancellation. Generally, not specific to the "desktop experience".
If yields are good enough we may not see 6core variation.
www.techpowerup.com/forums/threads/ryzen-7800x3d-196-with-bundle-at-microcenter.322094/
also, my apologies to the e-core dude in post three of that thread, I did not expect Intel to fall so hard at the time.
“If yields are good enough we may not see 6core variation for desktop DIY market. At least not in the beginning for like 1-2 years until they have enough stock of scrap silicon”.
Maybe they have APUs only for OEM market?
Or they will change it completely just like Intel did. But they still have the 9, 7, 5 designation so AMD also "needs" that too I guess.
MLID is quite often accurate since he does seem to genuinely have a lot of industry contacts, but this is still very much rumour/guesswork territory rather than a leak.
Also if you want to lecture someone, try to quote the whole post, not cut most of that post and then repost what the other person already posted as your own argument.
I wouldn't lose time replying to you about your... arguments that are mostly predictions and opinions that favor your fantasy..Probably they will copy the current Ryzen AI Max name. I believe next series will be Ryzen AI Max 400, not just for laptops but also desktops, to stay ahead of Intel.
AMD keeps coping the naming format from Intel and Nvidia believing that a similar naming with higher numbers will give them the edge in the eyes of the average consumer who knows close to nothing about CPUs. And it's not only AMD that does it. Intel abandoned the Core i naming after 15 years to copy Apple's naming.
I bet it would be the same on Zen 6 if they can. Having a lot of less than 8 cores volumes would probably mean they have a lot of defect.
There is way more chance that the Mid range is 1 full CCD, then we might have 1 or 2 sku bellow that are sold in volume, probably 10 and 8 cores. I wouldn't be surprised if there is just 1 really available in volume.
Same thing for 2 CCD system.
Also remember that if this leak is true, the CCD and I/O die are on silicon instead of on substrate. This mean an increase in manufacturing cost. The tradeoff is they would be able to deliver much improved performance for CCD to IOD communication. That mean the margin on a low core count CPU aimed at the lower end will probably be very low or unprofitable.